A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator

ABSTRACT


INTRODUCTION
The Delta-sigma (ΔΣ) ADC were widely used for signal acquisition and processing applications.Hence such types of ADCs were used as codec and hearing aids which require large dynamic range for signal paths [1][2][3][4].When compared with the Nyquist rate converters, ΔΣ ADC is easier to design as they do not require analog components with stringent parameters.Oversampling converter samples the input signal bandwidth and the need for an anti-aliasing filter is eliminated.With medium oversampling ratio and by increased sampling rate high-resolution ADC can be designed.This efficiently reduces the entire power consumption while maintaining the required resolution [5].Scaling of voltage is applicable to digital circuit design in reducing the heat dissipation at the trade-off of speed factor.Several techniques have been reported to address this problem such as body-driven circuits, SAR operation, sub-threshold operation [6][7][8][9] and zero crossing circuits [10,11] and the performance of these circuits were very less.The delta-sigma ADC is a very efficient structure with oversampling and noise shaping properties.The process scaling factor and bandwidth has been improved in continuous ΔΣADC.High performance analog circuits include op-amp less pipelined ADC [12,13], energy efficient successive approximation register (SAR) ADC [14,15] and digital calibrated technique [16,17].To process the signal in time domain voltage-controlled oscillators (VCO) play a major role [18][19][20][21][22][23][24].The VCO outputs introduce quantization error in VCO when the flip-flops are synchronized.
Several existing techniques in ΔΣ ADC architecture reduce the power consumption at the cost of speed [25][26][27][28][29]. Hence the performance of ADC can be improved by transferring the signal processing task to digital domain and by applying proper scaling methodology.In the proposed design, series-bilinear switch capacitor based VCO Quantizer is used to eliminate the harmonic distortion and non-linearity by frequency to current conversion-based linearization technique.The non-linearity of the developed and accomplished VCO based quantizers is improved by frequency to current conversion method.This paper is organized as follows.
The conventional ΔΣ ADC architecture, circuit designs with its layout are shown and explained in section 2. Section 3 describes the proposed work of series-bilinear based VCO.Section 4 describe the 4 result and discussion.Section 5 describes the conclusion.

CIRCUIT DESIGN OF CONVENTIONAL DELTA-SIGMA ADC 2.1. Two stage differential operational amplifier
Op-amp is the most important block of ADC and in CMOS technology the design of operational amplifiers is a challenge as the transistor channel length and voltage reduces.The advantages of the two-stage op-amp are the good gain, high output swing, low noise and good bandwidth over folded cascade op-amp [25].The differential gain structure consists of M1, M2, M3, and M4 against the structure of the conventional operational amplifier as in Figure 1.The input stage of the op-amp is constructed using M1 and M2 NMOS transistors.For the active load of input differential stage, M3 and M4 transistors are used.M7 is a load and M6 is a driver for current sink load inverter.The output of the M2 transistor was boosted using current source represented as M6 transistor [26].
The performance of two-stage CMOS op-amp is based on the width and length of the transistor.Care must be taken to assure that the transistors are operating in the saturation region and not in the triode region.This is because the triode region causes the transistor to behave in a non-linear fashion leading to poor transient response as well as the reduction of the overall gain [27].The layout of the two-stage amplifier is shown in Figure 2. The obtained area is 75.79*65.1µm²which has a total area of about 4933.9µm².The physical design steps including DRC check, LVS check, QRC Check and Post-layout simulation was done for the two-stage amplifier.

Loop filter
The loop filter of ΔΣ ADC provides the noise-shaping property.It suppresses the nonlinearity present in the VCO.To achieve a higher order noise shaping, the order of the loop filter must be increased.In this work, RC topology is chosen for its excellent linearity.In order to suppress the distortion, a high gain loop filter is required [28].Figure 3 shows the first order loop filter integrator.It is used because of its linearity and it is a fully differential circuit that converts square wave input into a triangular waveform.The input is given to the coupling capacitor.The high value of transconductance is achieved by adjusting the W/L ratio of the transistors.The circuit of the loop filter is shown in the Figure 3. Figure 4 shows the layout of the loop filter.The obtained area of the loop filter integrator is 59.06*137.94µm²which has a total area of about 8111.3µm².GDS-II file is also obtained for the layout.

Dynamic latch comparator
In dynamic latch comparators, two cross-coupled CMOS inverters are used for regeneration as in Figure 5.A clock is used to set the comparator in active or standby mode.The reset operation is achieved through the shorted transistor M6 between the two cross-coupled inverters.When the enable signal goes low, the circuit enters into the comparison phase.By adjusting the W/L ratio of the transistors, the high value of transconductance can be achieved [29,30].The major drawback of the dynamic latch comparator is the offset error caused by transistor mismatch and unbalanced charge residues [30].Figure 6 shows the layout of the dynamic latch comparator.The obtained area is 22.095*46.74µm² which has a total area of about 1032.7 µm.

Voltage controlled oscillator based quantizer
The most important building block of ADC is labelled as VCO based Quantizer.VCO produces a continuous time placed signal whose frequency is precisely corresponding to the input analog signal.The large value of transconductance is accompanied by regulating the W/L ratio of the transistors [31,32].It quantizes the signal on the individual stage and achieves the comparable digital output [33].There are mainly two types of building blocks for VCO placed ADCs named as counter based architecture and phase detector-based architecture [34].The VCO quantizer comprises of the multistage ring oscillator (RO), two arrays of DFFs and an array of XOR as shown in Figure 7.The power consumption obtained for VCO quantizer is 408.7µW.The layout of the VCO Quantizer is shown in Figure 8.The obtained area is 150.02*229.03µm² which has a total area of about 34359 µm².

Digital to analog converter (DAC)
The essential operation of DAC is to cause the digital output of ADC balanced to the analog input.Delta-sigma ADC uses multi-bit quantizer and multi-bit digital-to-analog (DAC) block to fix up the analog signal [35,36].Figure 9 shows that the layout of the Digital to Analog Converter (DAC).The obtained area is 15.28*33.58µm² of which the total area is about 513.1024 µm 2 .

PROPOSED SERIES -BILINEAR SWITCH CAPACITOR VCO BASED QUANTIZER
Switched capacitor circuits are used in the discrete signal processing applications [37].The operation of the switch capacitor circuit is based on the charging and discharging of charges in capacitors.The switched capacitor emulates the resistor and classified into three types named as parallel, series, and bilinear techniques.Switch capacitors are mainly used to minimize the chip area [38].Figure 10 shows the series-bilinear switch capacitor circuit.The proposed work used is the integration of a series capacitor switch and bilinear capacitor switch to reduce the non-linearity and harmonic distortion.The significance of the switch capacitor technique is to have a good dynamic range and accurate frequency.Accuracy is obtained from filter coefficients which are determined by capacitance ratio.In order to reduce the non-linearity, clock phases are introduced for charge transfer and non-overlapping clock phases.In the previously reported work, the VCO Quantizer is affected by linearity issues and noise distortion.In order to reduce the noise distortion, series-bilinear switched capacitor technique is proposed.The main difficulty in VCO-based Quantizer is the nonlinearity.Linearization technique used in this proposed work is FCC technique [39] (Frequency to the current converter) in which the harmonic distortions are reduced.The proposed VCO-based Quantizer uses two parasitic capacitances and two switches and it is insensitive to the applied voltage and current.Switched capacitor reduces the non-linearity issues using the linearization method.The proposed work consists of 4 switches.S1, S4 are odd Switch and S2, S3 even switches.Figure 11 shows the proposed circuit diagram of series-bilinear switch capacitor based low voltage integrator.
The series-bilinear transformation which is the simple continuous mapping from the S-plane to the Z-plane by the (1).
In the proposed work X2 and X3 are resistors; unswitched capacitors X5, X4, X1 perform as capacitive elements.
During Փ2, capacitors X2, X3 are discharged.During Փ1, X5, X4, X1 are charged and not losing the charge during Փ2.The equivalent resistance of the series-bilinear switch capacitor circuit is (2).
TELKOMNIKA Telecommun Comput El Control  A power efficient delta-sigma ADC with series-bilinear switch capacitor… (D. S. Shylu) Where R is the resistance and C1 and C2 is the capacitance of the Series-Bilinear switch capacitor circuit.
The flip-flops used in the VCO quantizer changes the VCO output at every clock edges.The output frequency of the VCO is sampled and is converted to current and is compared with the input current.The converted current is integrated to the loop filter.The layout of the 12-bit Delta-sigma ADC is shown in Figure 12.The obtained area is 136.7*143.2µm² of which the total area is 19575µm².quantizer is 408.7 µW with a sampling frequency of 100 kHz and a Vp-p of 1.2 V.The ADC is designed in a 90nm CMOS process and achieves 71.54 dB SFDR, 80.63 SNR, 11.56 ENOB, 2.68 mW power consumption for a 0.6 Vp-p differential input signal from a 1.2 V supply voltage.Figure 13 shows that the various specification parameters obtained for 12-bit Delta-sigma ADC.Table 1 shows performance comparision of proposed delta-sigma ADC with prior works [39][40][41][42][43][44].The power of 12-bit incremental delta-sigma ADC is reduced up to 65% when compared with conventional ADCs [45][46][47].

CONCLUSION
The proposed Delta-sigma ADC is used for high-resolution gain and stability of the quantizer.The designed op-amp achieves the gain of 41dB and consumes the power of 51.11µW from a 1-V supply.The ADC saves power by sharing a two-stage amplifier to perform signal summation.The loop filter produces the integrated output, which depends on the operational amplifier.The VCO quantizer is used as comparator circuit which quantizes the signal from the filter.The total power consumption of 12-bit ADC is 2.68mW.Simulation result shows that the proposed work 12-bit ΔΣ ADC consumes the power of 2.68mW and the total area occupied is 0.12mm 2 .The Post Layout simulation is done for all the blocks and GDS-II file format has been obtained for 12-bit incremental delta-sigma ADC .Based on the other reported ADCs in the literature it is found that the designed 12-bit Delta-sigma ADC with the new proposed VCO has less power consumption and less core area which make it suitable for various applications

Figure 5 .
Figure 5. Dynamic latch comparator Figure 6.Layout of the dynamic latch comparator

Figure 9 .
Figure 9. Layout of the DAC

Table 1 .
Performance comparision of proposed delta-sigma adc with prior works