An enhanced broadband class-J mode power amplifier for 5G smart meter applications [version 1; peer review: awaiting peer review]

Background: With the tremendous increase in the usage of smart meters for industrial/ household purposes, their implementation is considered a crucial challenge in the Internet of Things (IoT) world, leading to a demand for emerging 5G technology. In addition, a large amount of data has to be communicated by smart meters efficiently, which needs a significant enhancement in bandwidth. The power amplifier (PA) plays a major role in deciding the efficiency and bandwidth of the entire communication system. Among the various modes of PAs, a newly developed Class-J mode PA has been proven to achieve high efficiency over a wide bandwidth by maintaining linearity. Methods: This paper proposes a Class-J mode PA design methodology using a CGH40010F-GaN device that operates at a 3.5 GHz frequency to meet the requirements of 5G wireless communication technology for the replacement of existing 4G/LTE technology used for advanced metering infrastructure (AMI) in smart grids. This research's main objective is to design the proper matching networks (M.Ns) to achieve Class-J mode operation that satisfies the bandwidth requirements of 5G smart grid applications. With the target impedances obtained using the load-pull simulation, lumped element matching networks are analyzed and designed in 3 ways using the ADS EDA tool. Results: The simulation results reveal that the proposed Class-J PA provides a maximum drain efficiency (D.E) of 82%, power added efficiency (PAE) of 67% with 13 dB small-signal gain at 3.5 GHz, and output power of 40 dBm (41.4 dBm peak) with a power gain of approximately 7 dB over a bandwidth of approximately 400 MHz with a 28 V power supply into a 50 Ω load. Conclusion: The efficiency and bandwidth of the proposed Class-J PA can be enhanced further by fine-tuning the matching network design to make it more suitable for 5G smart meter/grid applications. Open Peer Review Reviewer Status AWAITING PEER REVIEW Any reports and responses or comments on the article can be found at the end of the article. Page 1 of 24 F1000Research 2021, 10:1099 Last updated: 14 DEC 2021

Introduction described in the Methodology section. The schematic Class-J PA circuit simulation results as per the design methodology and their comparison with similar recent works are presented in the Results and Discussion sections. Finally, the advantages and limitations of this proposed research work are detailed in the Conclusions.

Methods
From the theory of the Class-J operation mode introduced and developed by S.C. Cripps, 19 the high-efficiency amplification in broadband can be obtained by terminating the output of transistor M 1 to appropriate fundamental (Z f0 ) and second harmonic (Z 2f0 ) optimal load impedances, as shown in Equations (1) and (2), at different frequencies over the desired bandwidth, as shown in Figure 2(a).
where R opt is the optimum resistance, which can be expressed as shown in Equation (3).
With these optimum load impedances presented, from Figure 1, we can observe that the drain voltage (V DS ) is boosted with a phase shift.
Thus, the phase shift and boost in drain voltage (V DS ) cause a slight overlap with drain current (I D ), making the Class-J power amplifier highly efficient. Although this waveform shows the feature of a switching mode PA, the Class-J mode PA can provide linearity similar to the Class-B or AB modes because of its non-switching mode of operation. Unlike in Class-B, harmonic traps are unnecessary, making it suitable for wideband 5G applications.
The various steps involved in the design methodology of the proposed Class-J PA are discussed, as illustrated in the flowchart shown in Figure 2(b).

Selection of the transistor and technology
As per the trend of designing a power amplifier, the Advanced Design System (ADS) tool was used to design, and a CREE Device model (CGH40010F) based on GaN technology was used for simulation. The CGH40010F GaN transistor is chosen based on the features mentioned in its datasheet to obtain the desired power output required for smart meter applications. The gate threshold voltage (V th ) and gate quiescent voltage (VG Q ) of the chosen (CGH40010F) GaN transistor can also be obtained from its datasheet. To obtain a Class-J PA mode, the load impedances to be presented to this transistor (M1) (i.e., (CGH40010F) GaN transistor) are calculated theoretically using Equations (1) and (2) and can be verified using the Class-J workspace in the ADS design tool.

Selection of the biasing Network
As per the design idea of the power amplifier for this work, the supply voltage V DD = 28 V and gate bias voltage V GG ffi V K (threshold voltage) (i.e., with a quiescent bias current of I q = 2% of Imax) are chosen based on the (CGH40010F) GaN transistor's (M 1 ) datasheet for biasing it through a fixed-bias network to operate as a Class-B PA to obtain a half-wave rectified drain current (I D ). With the use of the fixed-bias network shown in Figure 3(a), the DC-IV characteristics of the    CGH40010F GaN transistor are drawn, and the quotient (Q) or bias point is obtained by adjusting marker m2 on the load line to operate it in Class-B mode, as shown in Figure 3(b).

Stability analysis
After choosing the bias point of the transistor while designing the power amplifier, one of the most important considerations is that it should be unconditionally stable irrespective of the frequency under normal operating conditions. To maintain the PA's stability at low frequencies, a stabilization circuit with a resistor connected in series with the transistor gate terminal is employed based on the datasheet of the CGH40010F GaN transistor. This series resistance can stabilize the transistor across the entire range of desired frequencies. To ensure the unconditional stability of the PA, the main conditions to be satisfied are that the Rollet stability factor is more than unity (i.e., (K>1)) and the stability measure (b) is positive. The Rollet stability and stability measures can be calculated theoretically by Equations (4) and (5), respectively.
However, practically unconditional stability of the PA can be ensured using Network Analyzer for S-Parameters (SP_NWA) from simulation instrument components, and the stability factor and its variation w.r.t. frequency can be obtained with the use of measurement expression functions and data display templates in Advanced Design System (ADS) tool, as shown in Figure 4. Selection of optimum input and output impedances of the transistor Generally, the transistor's optimum input and output impedances used for a PA design can be obtained by conducting load-pull simulations with the reference source and load impedances chosen from its datasheet.
As we are designing a Class-J PA in this research work, the reference source impedance can be chosen from the transistor's datasheet (if not mentioned in the datasheet, we can take approximately (5+j*0 Ω) for any GaN device). The reference fundamental and second harmonic impedances can be calculated theoretically using Equations (1), (2) and (3).
The reference target optimum impedances required to obtain Class-J operation can be determined using the Class-J ADS workspace utility, which is developed with mathematical design equations based on the load line.
After choosing the bias (Q) point by adjusting the load line on DC-IV characteristics, which are obtained from the fixedbias network shown in Figure 3(b), and by keeping the Alpha (α) factor in Equations (1) and (2) as "zero (0)" on the slider, as shown in Figure 5, the fundamental is terminated to a resistive load and higher-order harmonics are terminated as short, which leads to the Class-B mode of operation.
The reference target optimum impedances required for Class-J operation can be obtained by moving the alpha factor (α) in Equations (1) and (2) from 0 to 1 on the slider in Figure 6. With this target fundamental and second harmonic load impedance, the drain voltage (V DS ) is boosted with a phase shift.

Load-pull analysis
To verify the target fundamental and second harmonic load impedances shown in Figure 6, which are obtained based on the load line, load-pull simulations on the stabilized transistor must be conducted by taking them as reference impedances using a one-tone load-pull instrument at constantly available source power in the ADS EDA tool, as shown in Figure 7.

Validation of optimum impedances obtained from load pull
After obtaining the optimum source, fundamental and second harmonic load impedances from the LOADPULL simulations, corresponding to the MAX PAE, they can be validated by presenting them directly to the transistor (Z S and Z L ) instead of 50 Ω termination at the source and load terminals, as shown in Figure 8.

Input and output matching network design
After validation of the optimum input and output impedances (Z S and Z L ), the next important step in the design is the realization of the input and output M. Ns to match them with the 50 Ω termination source and load terminals. As we use the ADS EDA tool for this research work, impedance matching networks can be designed using three methods: Smith chart utility, impedance match utility, and equation-based lumped element L and π-type matching networks. Initially, to design the input matching network, the Smith chart component (DA_smithchart1) is terminated with a source impedance of 50 Ω and the output impedance as the source impedance of the CGH40010F GaN transistor obtained from load-pull analysis. As the M. N needs to be designed at an operating frequency of 3.5 GHz, an S-parameter sweep is set up for the range of 3-4 GHz, as shown in Figure 9(a).
After setting up the S-parameter sweep, the source impedance is set as 50 Ω. The load impedance is set as the input impedance of the CGH40010F GaN transistor (i.e., obtained from the load-pull simulations) on the Smith chart utility, and the travel path from source impedance to the load impedance leads to an L-type input M. N, as shown in Figure 9(b).  The output M. N is designed in the same manner as the input M.N. Nevertheless, the Smith chart component (DA _smithchart1) is terminated with source impedance as the output impedance of the CGH40010F GaN transistor (i.e., obtained from the load-pull analysis). The load is 50 Ω, and the S-parameter sweep is set up as an input matching network for the range of 3-4 GHz, as shown in Figure 10(a).
After setting up the operating frequency, source, and load impedances on the Smith chart utility, the travel path from source impedance to load impedance leads to an L-type output matching network, as shown in Figure 10(b).
Initially, these matching networks are designed for a bandwidth of approximately 1 GHz with an operating frequency of 3.5 GHz (i.e., sub6 GHz). With the desired bandwidth and center frequency, the quality factor can be calculated as Q = f/BW. In Smith chart utility, this Q factor can be represented as Q circles. For this work, the M. Ns at input and output are designed with a Q-circle of 3.
Next, the matching networks to match the same input and output impedances (based on load-pull analysis) are represented using the Z2P_Eqn file with the 50 Ω source, and load terminations are designed using the L.C. bandpass match smart component using an impedance matching utility, as shown in Figure 11(a).        After setting up the range of frequencies (i.e., 3-4 GHz), the source and load impedances of approximately 10-14 matching network topologies are designed for input and output matching in impedance matching utility, from which the network topologies with fewer passband errors after optimization are chosen, as shown in Figures 11(b) and 11(c).   Later, lumped element L-type input and π-type output M. Ns to match the same input and output impedances (obtained from load-pull simulations) with the 50 Ω source and load terminations are designed using basic L-type and π-type impedance matching network design equations with an operating frequency of 3.5 GHz and a Q-factor of 3 by setting up an S-parameter sweep for the range of 3-4 GHz, as shown in Figure 12.
Once the matching networks are designed, all topologies are placed at the input and output of the stabilized transistor to match the optimum Z S and Z L with the 50 Ω termination at the source and load terminals to complete the PA design, as shown in Figures 13, 14 and 15, respectively.
The output parasitic capacitance C DS of the transistor at higher-order harmonics is considered a short circuit. Once the OMN is designed, the capacitive reactance to the load-line resistance ratio [X CDS /R L ] needs to be calculated. Suppose this ratio is (<=) 1; then, the matching network design is considered ideal. However, this ratio can also be above unity based on the technology and frequency of the device used in the design.

Results
The Class-J PA is designed using a CGH40010F transistor with GaN technology in the Advanced Design System (ADS) EDA tool. Initially, after obtaining the bias (Q) point from the D.C., the stability analysis is performed on the CGH40010F GaN transistor with an S.P. network analyzer circuit, as shown in Figure 4. The unconditional stability of the device over the desired range of frequencies can be confirmed by checking the result on the stability factor and measuring the analysis represented using Figure 16 and Table 1. It is observed that the stability factor is >1, and the stability measure is >0, which ensures that the GaN device is unconditionally stable over the desired frequency range, i.e., (3-4) GHz.  After checking the device's stability, the optimum impedances required for the Class-J PA can be obtained by conducting load d pull simulations, as shown in Figure 7, with reference to the target source and load impedances that are obtained from load-line analysis, as explained in step 4 of the Methodology section. The optimum source/input impedance obtained from the load-pull analysis is 6.315+j*13.787, and the load/output impedance obtained is 16.151-j*0.970, corresponding to the maximum power delivered (Pdel_dBm_MAX), as shown in Figure 17.
Similarly, the optimum source/input impedance obtained is 6.322+j*14.053, and the load/output impedance obtained is 16.212+j*4.793, corresponding to the maximum PAE of 66%, as shown in Figure 18.
From the results of load-pull analysis, the optimum input and output impedances corresponding to the maximum PAE are chosen for the Class-J PA design and tabulated by comparison with the target source and load impedances obtained from load-line analysis-based mathematical design equations, as shown in Table 2.
Before validating the optimum source and load impedances, the PA is terminated to a 50 Ω source and load terminals and the corresponding performance parameters, as shown in Figure 19.  Figure 17. Optimum input and output impedances to obtain the maximum power delivered. Figure 19 shows that the performance parameters such as power delivered, large-signal and small-signal gains, D. E, and PAE are very low, as the CGH40010F GaN transistor does not terminate to optimum impedance values.
By terminating the transistor with the optimum impedance values obtained using load-pull simulations corresponding to the maximum PAE, harmonic balance S-parameter simulations are validated by running, as shown in Figure 8, and the respective performance parameters are shown in Figure 20.   From Figure 20, the performance parameters such as power delivered, large-signal and small-signal gains, drain efficiency and PAE are improved and nearly equal to the values obtained from load-pull simulations, as the input and output impedances of the CGH40010F GaN transistor are terminated to optimum impedance values. In addition, the reflection coefficients S (1,1) and S (2,2) are not as expected.
After validation of optimum impedances obtained from load-pull analysis, the M. Ns are designed as explained in step 7 of the Methodology section and placed at the respective input and output terminals of the PA, as Smith chart components are shown in Figure 13. Finally, these matching network elements are optimized and updated using an optimization tool in ADS, as shown in Figure 21.
After optimizing the performance parameters such as power delivered and large-signal and small-signal gains, PAE and D. E are shown in Figure 22. The reflection coefficients S (1,1) and S (2,2) are obtained as expected with the optimization of input and output matching networks.  The matching networks that are designed using L.C. bandpass match with the impedance matching utility, as explained in step 7 of the Methodology section, are placed at respective input and output terminals of the PA, as shown in Figure 14.
Then, these matching network elements are optimized and updated using an optimization tool in ADS, as shown in Figure 23.
After optimizing the performance parameters such as power delivered and large-signal and small-signal gains, PAE and D. E are shown in Figure 24. The performance parameters are improved slightly with the optimization of the matching networks that are designed using the impedance matching utility.
The matching networks that are designed using basic L-type input and π-type output matching design equations, as explained in step 7 of the Methodology section, are placed at the input and output terminals of the PA, as shown in Figure 15, and then these matching network elements are optimized and updated using an optimization tool in ADS, as shown in Figure 25.  After optimizing the performance parameters such as power delivered and large-signal and small-signal gains, PAE and D. E are shown in Figure 26. The performance parameters are obtained as expected with the optimization of input and output matching networks.
All the numerical values of performance parameters such as power delivered (Pdel_W, Pdel_dBm_MAX) in watts and dBm, large-signal gain (LS_Gain_dB), PAE and D. E (Deff) that are shown in Figures 19, 20, 22, 24, and 26, corresponding to without and with three matching topologies, are computed with many equations using the "MeasEqn" of the harmonic balance HB simulator. The load voltage is plotted as the spectrum in dBm, and intrinsic voltages/currents are plotted as time-domain signals using an (HB) simulation controller in ADS. The desired half-rectified intrinsic drain voltage and currents with small overlap that represent the Class-J mode of operation were obtained, and reflection coefficients S (1,1) and S (2,2) > -10 dB over a frequency range from (3.3-3.7) GHz were observed from Figure 26. The comparison of the performance parameters of the Class-J PA with and without matching networks obtained for different source and load terminations is shown in Table 3.
The above comparison table shows that among the 3 methods used for matching networks, the Class-J PA with L-type input and π-type output matching networks exhibits expected performance parameters that are obtained from load-pull simulations (i.e., 66% of PAE and 40 dBm of max power output), as shown in Figure 18.
To validate the variation in the performance parameters with respect to the input power sweep, HB simulations were performed on the proposed Class-J PA by taking the available source power (Pavs_dBm) as the sweeping parameter. Figure 27 shows the simulation results of important performance parameters such as drain efficiency, PAE, large-signal gain, and power delivered corresponding to the available source power (Pavs_dBm) sweep. These results demonstrate    Similarly, HB simulations were performed to validate the performance parameter variation of the proposed Class-J PA with L-type input and π-type output matching networks with respect to the input RF frequency, and the corresponding results are displayed in Figure 28. These results reveal that a power output above 40 dBm with a power gain of approximately 7 dB over a bandwidth of approximately 400 MHz (i.e., 3.3 GHz to 3.7 GHz) and max PAE and D. E of 67% and 82%, respectively, are obtained at a 3.5 GHz center frequency.

Discussion
Finally, the improved performance parameters of the proposed Class-J PA with L-type input and π-type output matching networks are compared with similar Class-J PAs in the literature. [30][31][32][33][34] As these PAs were designed at different frequencies and technologies, it is difficult to compare their performances. However, it can be noted that the Class-J PA design is proposed with a compact transmission line-based output matching network (OMN) in 30 that uses the same transistor technology (GaN) of this work to obtain broadband and highly efficient amplification and achieves a maximum drain efficiency of 75%. Although our proposed PA is designed at different frequencies, its bandwidth is the same as that of this PA, and its transmission line-based M. Ns use a large chip area compared to the M. Ns of our work. A microwave Class-J PA for Wi-Fi IEEE802.11a Bluetooth applications designed with a methodology similar to that of this work in the same ADS EDA tool is presented in, 31 which uses a GaAs transistor as an active device but achieves a power output of 21 dBm and D. E of 69%. A fully integrated Class-J PA designed at 5 GHz for WLAN 802.11ax applications was presented in 32 that uses GaN on SiC technology with the same V dd=28 V to provide a maximum PAE of 55% and output power of 38 dBm, and it was mentioned that the performance of this PA can be enhanced further by employing DPD. However, the gain of this PA is high compared to our work, as it is designed as a multistage PA. A Class-J PA designed for X-Band is presented in. 33 It uses the active load modulation technique, facilitates the PA's integrated implementation by eliminating the doubler and filter networks of conventional Class-J2 PAs, and achieves a drain efficiency of 71% and a PAE of 50%. However, the broad B.W. is not achieved because of harmonic tuners, and the auxiliary network used for phase shifting may need additional circuitry and space. A Class-J PA design with a novel direct M. N synthesis technique for broadband operation is presented in. 34 The PAE and output power (dBm) are almost the same at the frequency (3.5 GHz) of our proposed work. Although the synthesis technique is novel, the transmission line-based MNs may occupy a large chip area. In addition, an integrated Class-J PA using CMOS technology is presented in, 22 in which the effect of knee voltage is considered for deriving modified design equations. However, the staked FET must be used for implementation because of the CMOS PA's low breakdown voltage, whereas our work uses a GAN device with a high breakdown voltage. The performance comparison discussed thus far is summarized in Table 4. The PAE and DE of this work are better than those of other works shown in Table 4.

Conclusions
A 3.5 GHz Class-J PA design with lumped element-based input and output matching networks that are suitable for 5G smart meter/grid applications is presented in this paper. The proposed Class-J PA design methodology is demonstrated in a stepwise manner. It is observed that with a small overlap between the intrinsic half-wave rectified current and voltage waveforms at the drain, this Class-J mode PA can be as linear as Class-B or AB modes because of its non-switching mode of operation. From the simulation results, we conclude that the proposed Class-J PA obtains a maximum drain efficiency of 82%, which is better than similar Class-J PAs reported in the literature. A PAE of 67% with a 13 dB small-signal gain at 3.5 GHz and an output power of 40 dBm (41.4 dBm peak) with a power gain of approximately 7 dB over a bandwidth of approximately 400 MHz (i.e., 3.3 GHz to 3.7 GHz) are achieved with no harmonic traps, unlike in Class-B mode PAs, which makes this Class-J PA superior to other PA modes and more appealing for emerging wireless communication networks used for AMI of smart meters in 5G smart grids. However, the PAE and BW of the proposed Class-J PA can still be improved by fine-tuning the designed matching networks. This work is in progress to achieve desired specifications of 5G smart grid applications.

Data availability
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Author contributions
Mr. Nagisetty Sridhar-original drafting of manuscript preparation, Dr Chinnaiyan Senthilpari-validation and Supervision, Dr. Mardeni R-cosupervision. All the authors agreed to the final version of this manuscript.