Nanosheet integration of induced tunnel field-effect transistor with lower cost and lower power

Nanosheet transistors are poised to become the preferred choice for the next generation of smaller-sized devices in the future. To address the future demand for high-performance and low-power computing applications, this study proposes a nanosheet structure with a vertically stacked design, featuring a high ION/IOFF ratio. This Nanosheet design is combined with an induced tunnel field-effect transistor. By utilizing SiGe with a carrier mobility three times that of Si and employing a line tunneling mechanism, the research successfully achieves superior Band to Band characteristics, resulting in improved switching behavior and a lower Subthreshold Swing (SS). Comparative studies were conducted on three TFET types: Nanosheet PIN TFET, Nanosheet Schottky iTFET, and Fin iTFET. Results show that the Nanosheet PIN TFET has a higher ION/IOFF ratio but poorer SSavg values at 47.63 mV/dec compared to the others. However, with a SiGe Body thickness of 3 nm, both Nanosheet iTFET and Fin iTFET exhibit higher ION/IOFF ratios and superior SSavg values at 17.64 mV/dec. These findings suggest the potential of Nanosheet iTFET and Fin iTFET for low-power, lower thermal budgets, and fast-switching applications.


Introduction
As Moore's Law continues to evolve, the pursuit of faster switching speeds, lower power consumption, and smaller size variations has driven transistor technology through successive generations, transitioning from traditional planar transistor (Planar FET), nanowire, FinFET, to nanosheet.Among these advancements, nanosheets exhibit remarkable design flexibility, allowing the channel width to increase for enhanced current flow or decrease to limit power consumption.Stacked nanosheet transistors have been confirmed as the primary component structure for 3 nm technology nodes and smaller advanced technologies.Compared to FinFET, they demonstrate superior electrostatic characteristics and short channel control, making them the mainstream application for TSMC and Samsung in the 3 nm structure [1,2].
However, Nanosheets also bring along significant challenges, such as the trade-offs between transistor switching speed, power consumption, process complexity, and cost.This trade-off is closely related to the channel width, commonly

Research
Discover Nano (2024) 19:108 | https://doi.org/10.1186/s11671-024-04036-2referred to as W eff .Larger widths imply the ability to drive more current, facilitating quicker transistor on-off transitions, but they also necessitate a more complex and expensive manufacturing process [3].Despite Nanosheets becoming the mainstream application for TSMC and Samsung in the 3 nm architecture, MOSFETs still face challenges in overcoming the thermal limitation (thermal constraint) of 60 mV/decade SS at room temperature (300 K) and the difficulty in reducing the power supply voltage (V D ) below 0.5 V [4].As the Internet of Things (IoT) and artificial intelligence (AI) chip technologies rapidly advance, the increasing demand for higher voltages becomes an undeniable challenge for future device power consumption.
In response to this, researchers propose Tunnel Field-Effect Transistor (TFET) that leverage their Band-to-Band quantum tunneling mechanism to overcome carrier Boltzmann distribution.These devices, in comparison to Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), offer advantages, enabling high performance under extremely low operating bias conditions, achieving low power consumption and rapid switching effects [5,6].
Normally, Tunnel Field-Effect Transistor (TFET) exhibits two tunneling current generation mechanisms [7].The first is "point tunneling", occurring at the source-channel interface, with its primary contribution confined to a small region.Due to the limited tunneling area, the Band-to-Band effect is restricted, resulting in a Subthreshold Swing (SS) that does not reach an ideal level.The second is "line tunneling", located in the source region overlapping with the gate.As the region where Band to Band begins resembles a line, this component is referred to as "line tunneling".Compared to point tunneling, line tunneling has a broader tunneling area, and the current is directly proportional to both the channel width (W) and channel length (L) of the device, effectively improving subthreshold swing (SS) [8][9][10][11][12][13][14].In this work, we will discuss and compare the results obtained from these two tunneling mechanisms.
We have also made improvements in addressing the expensive manufacturing processes by adopting a SiGe (70% Si and 30% Ge) monolithic material for stacking.The source metal is configured as a Schottky contact, forming different Schottky barrier heights by utilizing metals with distinct work functions.This leads to the inversion of a thinner carrier inversion layer, replacing the need for doping and thermal annealing associated with traditional material stacking.Simultaneously, this approach expands the area on the source side, thereby increasing the linear tunneling area between the gate and source, further enhancing the device's performance [5].
Our proposed iTFET utilizes Schottky contacts to achieve a total line-tunneling dominated TFET.In contrast to traditional TFETs that require doping to establish p-type and n-type regions for P-I-N or P-N-N structures, iTFETs use a single piece of N-substrate with uniform doping concentration.Due to the band bending, thermal activation creates an inversion layer, converting the Source region into P-type, thus forming an overall PN structure [15].
In Sect.2, we will present the device design, manufacturing steps, and simulation methods.In Sect. 3 will discuss the circuit characteristics under various parameter variations and simulation results.Finally, Sect. 4 will summarize the conclusions of this study.

Device design and simulation method
We conducted a comparison of Nanosheet PIN TFET, Nanosheet iTFET, and Fin iTFET with body thicknesses of 5 nm and 3 nm.Figure 1 shows the SiGe Body thickness of 5 nm for Nanosheet PIN TFET, Nanosheet iTFET, and FinFET iTFET.In Fig. 2, the SiGe Body thickness is depicted as 3 nm.
Figure 3 shows the cross-sectional diagrams of the Nanosheet PIN TFET and Nanosheet iTFET.Various device parameters are presented in Table 1.By replacing traditional Si with SiGe, having a carrier mobility three times that of Si, we achieved superior Band-to-Band characteristics [16].A PN junction can be formed by utilizing the Schottky contact characteristics of a metal-semiconductor contact with different work functions.To enhance the reliability of the comparison, we employed a uniform overall structure with dimensions of 55 × 25 × 55 (nm 3 ) and 55 × 33 × 33 (nm 3 ) for length, width, and height, respectively.Although the gate channel length of Nanosheet PIN TFET is 35 nm, the same as the other two, the presence of additional doping regions increased its length by 20 nm, resulting in overall dimensions of 75 × 25 × 55 (nm 3 ) and 75 × 33 × 33 (nm 3 ).This is a drawback of Nanosheet PIN TFET, requiring a larger volume and incurring higher process costs.
Even with efforts to use the same lengths for reliable device comparison, unavoidable adjustments may arise, such as when the body thickness is adjusted from 5 to 3 nm.Considering process-related factors, the gate oxide thickness (t ox ) must also be adjusted with the change in body thickness.Furthermore, in Nanosheet iTFET and Fin iTFET, we employed a uniform doping concentration.In contrast, Nanosheet PIN TFET requires different doping concentrations at various locations to achieve the desired device characteristics.When selecting doping concentrations, we specifically considered High-field saturation mobility models, Auger recombination model, and considering minute fabrication details, we introduced quantum confinement effects.To ensure the accuracy and feasibility of the simulations, we utilized experimentally fabricated Si/SiGe heterojunctions, considering TFETs that exhibit both line and point tunneling simultaneously [5].Model calibration for the simulations is illustrated in Fig. 4.
The fabrication process for the stacked SiGe nanosheet iTFET is shown in Fig. 5.To begin, multi-layer SiGe/Si/Ge stacks, each with 5 nm Ge 0.3 Si 0.7 and 5 nm Si, were grown in a reduced-pressure chemical vapor deposition (RPVVD) chamber in Fig. 5a.Following the stack growth, fin arrays patterns were precisely created utilizing the spacer image transfer (SIT) technique, achieving a resolution beyond that of advanced photolithography.This meticulous method guaranteed the accurate definition of the intended fin structures in Fig. 5b.To define the fins, fin etching was performed, shaping, refining the structures to the required specifications in Fig. 5c.Shallow trench isolation (STI) was introduced, while a SiO 2 with a high aspect ratio process (HARP) was deposited to enhance the overall structure, providing essential isolation for subsequent transistor components.To reveal the fin, diluted hydrofluoric acid (DHF) was used to perform a SiO 2 etching process in Fig. 5d.A dummy gate stack was formed on the fins during the execution of dummy gate formation in Fig. 5(e).SiO 2 spacers were carefully formed in Fig. 5f.S/D cavity etching and partial etching of Ge and Si were performed in Fig. 5g.A one-sided inner spacer was meticulously achieved by depositing a thin layer of SiNx and employing the Reactive Ion Etching (RIE) process in Fig. 5h.The Ge 0.3 Si 0.7 epitaxy process with in-situ doping was followed by the epitaxial growth of the source and drain regions in Fig. 5i.ILD0 deposition was carried out in Fig. 5j.Dummy gate was promptly eliminated through immersion in tetramethylammonium hydroxide in Fig. 5k.The release of Ge Nanosheet (NS) channels through 1 × 10 18 cm −3 Schottky barrier hight (φb) 0.9 eV Fig. 4 TCAD model calibration using experimental data [17] selective etching in Fig. 5l.Source metal deposition in Fig. 5m.Source metal partially removed in Fig. 5n.Selective etching released Si Nanosheet (NS) channels in Fig. 5o.The multilayer High-K Metal Gate (HKMG) film stacks were applied using an Atom Layer Deposition (ALD) method.In Fig. 5p.Chemical mechanical planarization (CMP) was applied, smoothing, and refining the device's surface in Fig. 5q.ILD deposition was carried out in Fig. 5r.Finally, metal deposition and contact were established in Fig. 5s [18][19][20][21].
Compared to traditional devices, Nanosheet iTFET exhibits a larger overlap area between the gate and source metal within the same volume, as illustrated in Fig. 6.This is advantageous for the iTFET, which relies primarily on the line tunneling mechanism, where tunneling current is proportional to the width (W) and length (L).Therefore, increasing the overlap area allows the iTFET to demonstrate excellent circuit characteristics [22,23].To address this, we further explore Nanosheet iTFET and Fin iTFET, which primarily utilize the line tunneling mechanism, to achieve a smaller SS.

Comparative analysis of three semiconductor devices and the benefits of stacking
Nevertheless, the I ON of these two devices is relatively lower.When the SiGe Body thickness is reduced to 3 nm, Nanosheet iTFET and Fin iTFET, benefitting from a thinner substrate, showcase a slight increase in I ON due to enhanced tunneling capabilities.This improvement successfully mitigates the issue of lower I ON .In contrast, Nanosheet PIN TFET exhibits a slight decrease in I ON and a minor ambipolar effect, leading to an increase in leakage current and a reduction in I ON /I OFF ratio.Therefore, Nanosheet iTFET and Fin iTFET perform better at a SiGe Body thickness of 3 nm, making them more ideal choices for smaller sizes.Additionally, when the SiGe Body thickness is 5 nm, the SS avg for Nanosheet PIN TFET is 47.63 mV/dec, while for Nanosheet iTFET and Fin iTFET, it is 22.48 mV/dec and 20.22 mV/dec, respectively.At a SiGe Body thickness of 3 nm, the SS for all three structures shows a slight improvement.A comparative analysis of the three components in Table 2. Figure 9 shows the current variation plots for Nanosheet PIN TFET and Nanosheet iTFET at different SiGe Body thicknesses and varying the number of sheets.It is observed that with an increase the number of sheets, both Nanosheet PIN TFET and Nanosheet iTFET exhibit a rising trend in I ON current.Thus, by employing stacking, we effectively enhance the I ON performance of TFET, addressing the relatively lower I ON scenario while achieving lower SS and reduced power consumption.
Upon further increasing the number of sheets, we conducted observations on Nanosheet PIN TFET and Nanosheet iTFET in Fig. 10a.Increasing the number of sheets indeed leads to an increase in I ON , but it also comes with an increase in I OFF .However, it's important to consider the overall change in I ON /I OFF ratio.Even if both I ON and I OFF increase, if their increase is relatively small, the overall change in I ON /I OFF ratio won't have a significant impact on device performance.Therefore, increasing the number of sheets can effectively address the issue of low I ON in TFETs while maintaining a good I ON /I OFF ratio, as depicted in Fig. 10b.We calculated the average I ON gain per stack for each component, revealing that although the I ON gain per stack does not linearly increase with the number of stacks, it also does not decrease in Figure 12a shows the current variation of Nanosheet iTFET and Fin iTFET with different numbers of stacked layers under the same volume.For example, with SiGe Body = 5 nm, in the case of 2 stacked layers, the dimensions are 55 × 25 × 25 (nm 3 ), and for 4 stacked layers, the dimensions are 55 × 25 × 55 (nm 3 ).In this comparable scenario, we examined whether the benefits of stacking surpass those of Fin iTFET.The results indicate that for SiGe Body = 5 nm, the average benefits of Fin iTFET are greater than those of Nanosheet iTFET.Figure 12b also indicates that there won't be significant changes in I ON /I OFF .However, for SiGe Body = 3 nm, Nanosheet iTFET exhibits better average benefits in Fig. 13.This is because Nanosheet iTFET already performs optimally among these three components at SiGe Body = 3 nm.

Optimization and analysis of device parameters
Figure 14 shows the current variation plot of Nanosheet iTFET at different SiGe Body concentrations.Due to the operation of TFET being based on quantum tunneling effects, electrons tunnel through the band bending.We observe that with the increase in SiGe Body concentration, the height of the barrier changes, allowing more electrons to easily tunnel across the barrier.This results in the device achieving higher I ON in the on-state.In the off-state, as the concentration increases, the device exhibits superior control, achieving lower I OFF and consequently reducing the overall SS.However, when the concentration becomes too high, despite the increase in I ON in the on-state, it also generates a significant amount of carrier tunneling, markedly increasing the leakage current, as shown in Fig. 15.Therefore, we choose 1 × 10 18 cm −3 as the substrate concentration for the device, as it performs better in terms of I ON /I OFF and SS avg , as detailed in Fig. 16.
Figure 17 shows the current variation with different Schottky barrier heights (φb).To achieve Schottky contact, we observe that when φb < 0.7 eV, thermal electron injection is prominent.Conversely, when φb > 0.7 eV, the dominant Fig. 13 The total on current (I Dsat ) per average layer versus the number of sheets.In the on-state, with both components having the same volume, the current efficiency brought by each layer's stack number mechanism in the device gradually transitions from thermal electron injection to tunneling, allowing SS to decrease below 60 mV/dec, as shown in Fig. 18.With the increase in φb, both I ON and SS exhibit superior performance [24].When the band bending reaches a certain degree, leakage current also starts to increase due to tunneling in the off state.It can be observed that when φb = 0.9, the tunneling effect on leakage current becomes more pronounced, resulting in a slightly higher I OFF compared to φb = 0.8.This suggests that an increase in φb does not necessarily lead to an absolute improvement in device performance in Fig. 19a, b.
Figure 20 shows the current variation at different SiGe Body thicknesses.As the Nanosheet iTFET primarily adopts the line tunneling mechanism, a thinner substrate not only reduces the device's volume but also shortens the tunneling  distance between the Gate and Source, enhancing the Band-to-Band tunneling effect and thus improving device performance.Therefore, the choice of substrate thickness is crucial for TFET performance.We observe that when the SiGe Body thickness is 3 nm, it not only exhibits optimal I ON /I OFF but also achieves the lowest SS and minimal volume.Conversely, when the SiGe Body thickness > 10 nm, the tunneling effect becomes less favorable, leading to an SS exceeding 60 mV/ dec, which compromises the TFET's advantage in rapid switching compared to MOSFET in Fig. 21.

The non-ideal effects of the device and improvement
The presence of interface traps has been observed to reduce the conduction current in tunneling TFETs, primarily relying on the tunneling interface lateral electric field peak.Since interface traps are only present on the interface at channel-drain tunneling junction only, the on-current is likely unaffected by interface traps.However, the ambipolar conduction induced by the motion of charged carriers at the output tunneling interface is significantly influenced by interface traps.It can be noted that both points tunneling-dominated PIN TFET and line tunneling-dominated Nanosheet iTFET are affected by traps, as illustrated in Fig. 22a-c.To mitigate the impact of traps on device performance, apart from employing High-K materials proposed by others in this device, we have suggested several methods to ameliorate the effects of traps [25][26][27].
Since interface traps typically occur at the interface between HfO2 and SiGe Body, with the increase in interface trap density, the negative charge density at the interface increases, thereby increasing the electron concentration at the interface.This situation induces band bending in the interface tunneling oxide.The introduction of traps creates new tunneling channels for charge carriers to cross the bandgap, resulting in leakage current occurring even in the off state due to tunneling.Therefore, the occurrence of tunneling phenomena leads to an increasing trend in the leakage current profile.We first focus on the discussion of SiGe Body [28,29].We varied the SiGe Body thickness of the Nanosheet iTFET from 5 to 15 nm.The results show that at a SiGe Body thickness of 5 nm, interface traps have a noticeable impact on the device.However, as the SiGe Body thickness increases, the influence of traps gradually diminishes, especially when SiGe Body = 15 nm, the device is almost entirely unaffected by traps, as shown in Fig. 23a-d.It's essential to note that since our device is primarily line tunneling-dominated, increasing the SiGe Body thickness reduces the device's line tunneling control capability.Besides increasing the device volume, the subthreshold swing also increases accordingly.As mentioned earlier, when SiGe Body > 10 nm, the SS exceeds 60 mV/dec.Considering these results, increasing the SiGe Body thickness is not an effective way to mitigate the impact of traps.
While increasing the drain length to lengthen the distance between the gate and drain can effectively reduce I OFF , which is a well-known technique [30], it becomes evident that adjusting the drain length is not an effective means to mitigate the impact of traps, especially when considering the presence of interface traps.This is illustrated in Fig. 24.Clearly, the adjustment of drain length is not an effective approach to address the influence of traps.
By altering the source metal, we indirectly adjusted the Schottky barrier height (φ b ) [17].At (φ b ) = 0.9 eV, the device achieves better I ON /I OFF and lower SS.However, when considering the non-ideal effects of interface traps, increasing (φ b ) not only effectively enhances I ON /I OFF but also has a significant impact on traps in Fig. 25a-c  We applied (φ b ) = 0.8 eV to all three devices and conducted a device analysis under different interface trap conditions in Fig. 26.The results indicate that, without considering interface traps, the PIN TFET using the point tunneling mechanism exhibits superior I ON /I OFF .However, with the increase in interface trap concentration, Nanosheet iTFET and Fin iTFET, utilizing the line tunneling mechanism, outperform in terms of I ON /I OFF, as shown in Fig. 27a.Regarding subthreshold swing (SS), all three devices show an increase as the interface trap concentration rises.Even at a relatively high interface trap concentration of 1 ×10 12 , PIN TFET maintains an SS below 60 mV/dec, while Nanosheet iTFET and Fin iTFET demonstrate commendable performance with an SS of 33 mV/dec in Fig. 27b.
By comparing our device with stacked Nanosheet devices reported in recent years, our device demonstrates a lower subthreshold swing at lower power supply voltages in Table 3 and Fig. 28 [3,[31][32][33][34].While the I ON /I OFF ratio may be slightly lower compared to other reference literature, we believe that users can choose an appropriate number of stacking layers based on their specific I ON requirements, thus addressing the challenge of maintaining a low subthreshold swing while improving the issue of too low I ON /I OFF .

Conclusion
In this thesis, we employ a line tunneling mechanism and applying Nanosheet stacking method, combined with iTFET technology.This has successfully achieved superior Band-to-Band characteristics, lower subthreshold swing, and higher I ON .In terms of the fabrication process, using the line tunneling mechanism in iTFET allows Nanosheet iTFET to have a larger gate and source overlap area, compared to traditional Nanosheet MOSFETs of the same volume,

Figures 7
Figures7 and 8show the I D -V G characteristics of Nanosheet PIN TFET, Nanosheet iTFET, and Fin iTFET, respectively.When the SiGe Body thickness is 5 nm, the Nanosheet PIN TFET, utilizing the traditional point tunneling mechanism, exhibits a significantly higher I ON compared to the other two; however, this is accompanied by a larger subthreshold swing (SS).To address this, we further explore Nanosheet iTFET and Fin iTFET, which primarily utilize the line tunneling mechanism, to achieve a smaller SS.Nevertheless, the I ON of these two devices is relatively lower.When the SiGe Body thickness is reduced to 3 nm, Nanosheet iTFET and Fin iTFET, benefitting from a thinner substrate, showcase a slight increase in I ON due to enhanced tunneling capabilities.This improvement successfully mitigates the issue of lower I ON .In contrast, Nanosheet PIN TFET exhibits a slight decrease in I ON and a minor ambipolar effect, leading to an increase in leakage current and a reduction in I ON /I OFF ratio.Therefore, Nanosheet iTFET and Fin iTFET perform better at a SiGe Body thickness of 3 nm, making them more ideal choices for smaller sizes.Additionally, when the SiGe Body thickness is 5 nm, the SS avg for Nanosheet PIN TFET is 47.63 mV/dec, while for Nanosheet iTFET and Fin iTFET, it is 22.48 mV/dec and 20.22 mV/dec, respectively.At a SiGe Body thickness of 3 nm, the SS for all three structures shows a slight improvement.A comparative analysis of the three components in Table2.

Fig. 7 IFig. 8 ITable 2 Fig. 11 .
Fig. 7 I D -V G characteristic curves of the three devices with both SiGe Body thickness and gate oxide thickness set to 5 nm

Fig. 9 aFig. 10 aFig. 12 a
Fig. 9 a I D -V G characteristic curves of the PIN TFET, b of the Nanosheet iTFET, with varying SiGe Body thicknesses, as a function of increasing stack layers

Fig. 14 IFig. 15
Fig. 14 I D -V G characteristic curves for different SiGe body concentrations of the Nanosheet iTFET

Fig. 16 IFig. 17
Fig. 16 I ON /I OFF , SS avg , for different SiGe body concentrations of the Nanosheet iTFET

Fig. 18 I
Fig. 17 I D -V G characteristic curves for different Schottky barrier heights of the Nanosheet iTFET

Fig. 19 a
Fig. 19 a Band diagram, b Band-to-band generation for different Schottky barrier heights of the Nanosheet iTFET

Fig. 21 I
Fig. 21 I ON /I OFF , SS avg , for different SiGe body thickness of the Nanosheet iTFET

Fig. 23 I
Fig. 23 I D -V G characteristic curves with SiGe Body thicknesses of a 5nm, b 7nm, c 10nm, d 15nm, as a function of different interface trap densities of the Nanosheet iTFET

Fig. 26 I
Fig. 26 I D -V G characteristic curves of the three devices with different interface trap densities at Schottky barrier height = 0.8 eV

Table 1
The SiGe Body thickness is 5 nm/3 nm for device parameters