By the circuit of Phase-Locked Loop(PLL), the external system clock with high frequency accuracy but poor phase noise is converted into an internal clock signal with high frequency accuracy and low phase noise simultaneously. The internal clock source is coherent with the external source by the PLL as well. The effect of the PLL loop bandwidth on the phase noise of the output signal is analyzed emphatically through both simulations and measurements. Test results show that, at 100 Hz of loop bandwidth, the phase noise of the PLL output signal basically equals to that of the internal oscillator at 1 kHz away from the carrier. While at 500 Hz of loop bandwidth, the phase noise of the PLL output signal is decreased by 8 dB at the same place, compared to the internal oscillator phase noise, due to being affected by the loop filter. The phase noise of the proposed 100 MHz clock source is better than -147 dBc/Hz@1 kHz, which is improved by 12 dB than that of the external reference clock signal，and the frequency accuracy can reach up to 1×10-9.