A 20 ppm/°C Temperature Coefficient and High Power Supply Rejection Ratio Bandgap Reference Implemented in 90 nm CMOS Technology for Low Drop-Out Voltage Regulator Applications

This paper proposes a CMOS band gap reference voltage design in 90 nm CMOS technology for Low Drop-Out (LDO) voltage regulator applications, with a high Power Supply Rejection Ratio (PSRR), high accurate high order in the output and less temperature drift over wide temperature range for compensating LDO Voltage regulators. The band gap utilizes two circuit techniques CMOS in the same time to obtain stable reference output voltage. The design simulation is done at 1 V to 1.2 V in gpdk 90 nm CMOS technology using Cadence software. The voltage output of 0.750 V± 5 mV, the results leads to a temperature coefficient (TC) of 20 ppm/°C, power supply rejection of the circuit can reach 72 dB, the output reference voltage exhibits a variation of less than 2.5% during the entire experiment, when the variations of the temperature over [– 60 °C, 130 °C] and the active area of the circuit is 72 μm².