Memory Access Reduction for Field Programmable Gate Array-Speeded Up Robust Features Implementation
In the preceding FPGA-SURF implementation, researchers concentrate on applying parallelism onto the SURF multiple layers of the scale-space pyramid. This is possible since only the filter size of the SURF algorithm varies and the original image remains unchanged. However, they don't
look into the memory access problems which would hold back the execution speed of the FPGA-SURF implementation. This problem is proven by a software profiling analysis conducted in this paper. For that reason, further analysis is conducted and we discover that the SURF algorithm memory access
shows a significant redundant pattern that can be safely discarded. Based on the pattern, a design with reduced memory access is proposed.
Document Type: Research Article
Publication date: 01 February 2013
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