A Novel Direct Torque Control for Induction Machine Drive System with Low Torque And Flux Ripples using XSG

The conventional Direct Torque Control (DTC) is known to produce a quick and robust response in AC drives. However, during steady state, stator flux and electromagnetic torque which results in incorrect speed estimations and acoustical noise. A modified Direct Torque Control (DTC) by using Space Vector Modulation (DTC-SVM) for induction machine is proposed in this paper. Using this control strategy, the ripples introduced in torque and flux are reduced. This paper presents a novel approach to design and implementation of a high perfromane torque control (DTC-SVM) of induction machine using Field Programmable gate array (FPGA).The performance of the proposed control scheme is evaluated through digital simulation using Matlab\Simulink and Xilinx System Generator. The simulation results are used to verify the effectiveness of the proposed control strategy.


INTRODUCTION
Since its inception, the Direct Torque Control has gained popularity for induction machine drives. Indeed, the control variables that are the stator flux and torque are calculated from the quantities related to the stator without the intervention of mechanical sensor. The response of the DTC is fast, however it has some drawbacks such as notable torque and flux ripples and the variable commutation frequency behavior of the inverter. Many papers presented different approaches to minimize the flux and torque ripples [1]- [4]. In [1] and [3], electromagnetic torque and flux are controlled directly by the selection of a switching vector from a table selection. Nevertheless, the selected vector is not always the best one because only the sector is considered, where the flux space vector lies without considering its location.
To overcome the several disadvantages of DTC a new control technique called Direct Torque Control -Space Vector Modulated (DTC-SVM) [5]- [6] is developped. In this new method, the disadvantages of the DTC are eliminated. The DTC-SVM strategies are based on the same fundamentals as classical DTC; it provides dynamic behavior comparable with classical DTC.
In practice, the vector control algorithm for an induction machine is implemented utilizing digital signal processor (DSP). The DSP control procedure is performed sequentially; this may result in a slower cycling period if complex algorithms are involved. Employing field programmable gate array (FPGA) in implementing vector control strategies provides advantages such as simpler hardware and software design, rapid prototyping, hence fast switching frequency and high speed computation [7]- [8].
The paper devotes to a comparative study between the performances of two approaches: (i) Classical DTC (ii) DTC-SVM. These strategies are designed using Xilinx System Generator (XSG) and Matlab/Simulink software packages and implemented on FPGA controller.

BASIC PRINCIPLE OF DTC
The main idea of DTC is to recover the reduction of the ripples of torque and flux, and to have superior dynamic performances. Figure 1 present a possible schematic of Direct Torque Control. There are two different loops corresponding to the magnitudes of the stator flux and torque. The error between the estimated stator flux magnitude φ s and the reference stator flux magnitude φ s *is the input of a two level hysteresis comparator whereas the error between the estimated torque T e and the reference torque T e * is the input of a three level hysteresis comparator. The outputs of the stator flux error and torque error hysteresis blocks, together with the position of the stator flux are used as inputs of the switching table.
The stator voltage and stator current are calculated from the state of three phase (Sa ,Sb ,Sc) and measured currents (ia, ib, ic).
The developed electromagnetic torque T e of the machine can be evaluated by Equation (4): The stator flux vector is moving along a straight axis colinear to that of the voltage vector required by the inverter:

DTC SPACE VECTOR MODULATION
The DTC algorithm is based on the instantaneous values and directly calculated the gate signals for the inverter. The control algorithm in DTC-SVM is based on average values whereas the switching signals (Sa, Sb and Sc) for the inverter are calculated by space vector modulator [9]- [11].

Principle of Vector MLI
For each period of modulation of the inverter, the three phase voltages provided by the control algorithm can be expressed in a fixed reference linked to the stator, through their projections V sα and V sβ .
The inverter has six switching cells, giving eight possible switching configurations. These eight switching configurations can be expressed in the plane (α, β) by 8 vectors tensions.
Knowing that in the graduation phase voltages (Va, Vb, Vc) are represented in the plane by a vector V s . The principle of vector MLI is to project the desired stator voltage vector V s on the two adjacent vectors corresponding to two switching states of the inverter. The values of these projections provide the desired commutation times.

General Structure of the Control DTC-SVM
Most existing blocks in the control DTC-SVM are identical to those of control DTC as shown in the following figure (3). The new blocks will be discussed below.

Calculation of time of application of the status of the inverter
Each modulation period T mod of the inverter, the projected vector V s on the two adjacent vectors assures the switching time of calculation.
The key step of the SVM technique is the determination of T i and T i+1 during every modulation period T mod . To illustrate the methodology we consider the case where V s can be compounded by the active voltage vectors V 1 and V 2 . The projection of the reference voltage vector on V 1 and V 2 is illustrated in the following figure: The active voltage vectors V1 and V2 are given as follow: Expressing the voltage vector Vs in the graduation (α, β) we have: Expanding this equation it is possible to express the time T 1 and T 2 in terms of V sα and V sβ . The conduction time will be expressed as follows: To facilitate the calculations, we normalize the voltages Vsα and Vsβ by posing: Consequently, the duties expressions are given as follows: The space vector in sector 1 is shown in figure (5).The time duration of zero vectors is divided equally into (V0, V1, V2, V7, V2, V1, V0), whereas the time duration of each nonzero vector is distributed into two parts. This sequence can ensure that is one phase switches when the switching pattern switches, thus can reduce the harmonic component of the output current and the loss of switching devices.

SIMULATION AND RESULT
The DTC and DTC-SVM scheme for induction machine are simulated using Matlab/Simulink and Xilinx System Generator and their results have been compared. The machine parameters used for simulation are given in this

Simulink Model of Direct Torque Control
The simulation of DTC was conducted using Simulink\MATLAB. The inverter switching pulses are obtained from the switching table which decides the pulses from the error signals of torque and flux. The overall DTC model is shown in Figure 6.  Figure 7 illustrate the simulation block of the DTC-SVM control. The system is composed of the machine, PI controllers, three phase voltage source inverter, reference frame transformation blocks Concordia and Park. The Insulated-gate bipolar transistor IGBT switches are controlled using space vector modulation technique.

Simulink Model of Space Vector Modulated Direct Torque Control obtained with Xilinx System Generator
Initially, an algorithm is designed and simulated at the system level with the floating-point Simulink blocksets. A hardware representation of FPGA implementation is then derived using XSG. The XSG provides a bit-accurate model of FPGA circuits and automatically generates a synthesizable VHDL code for implementation in Xilinx FPGA. For DTC-SVM modeling, the blocks used are mostly multipliers, adders, Cordic sin cos, etc. The detailed steps are shown in the following diagram in Figure 9. The XSG design of proposed DTC-SVM is shown in Figure 10. The block Calcul_Vsalpha_Vsbeta is used to project the threephase voltages in the repository (α, β) by performing the processing Clarke as shown in Figure 10(a). The block SVM generates a series of pulses to be used subsequently to carry out the control signals used in the model of the inverter as shown in Figure 10(b) and 10(c). The XSG design of torque and flux estimator is shown in Figure 11 It is possible to see in Figure 13(a), (b), (c) an appreciable reduction of electromagnetic torque ripple has been obtained using the DTC-SVM. For the DTC, torque variation of the hysteresis band equal to 1.1. The high ripple observed in the DTC is reduced when we use the DTC-SVM, because in SVM, many vectors (IGBT states) are selected to adjust the flux and torque ripple in each sample time, whereas in DTC just one vector is selected to adjust ripple inside hysteresis bands of flux. Using SVM control provides the system with minimum ripple for flux as shown in Figure 14, where the flux ripple percentage is about 0.92%.
The DTC-SVM of induction machine presents the advanced performance to achieve tracking of the desired smooth circular trajectory of stator flux locus shown in Figure 15.  The best results are given by DTC-SVM using MATLAB\SIMULINK, this is due to the arbitrary choice of the number of bits at XSG.

FPGA SIMULATION RESULTS OF DTC-SVM
The above designed model is implemented using FPGA Editor. FPGA Editor reads the NCD file generated by the Map or Place & Route process, which contains the logic and routing of the design mapped to components, such as CLBs and IOBs.The internal structure of FPGA is shown in Figure 16. The result of the resources used is shown in the following table:

CONCLUSION
This paper has been devoted to the comparison between the performances of the DTC and DTC-SVM strategy. The steady state features of the induction machine as well as the transient behavior under both approaches have been commented and compared. The simulation result clearly indicates the high performance of DTC-SVM. The proposed high performance scheme is designed using XSG and Matlab/Simulink blocksets and implemented on Xilinx Virtex 5 FPGA. Numerical simulations have been carried out showing the advantages of the DTC-SVM with respect to the DTC. This work is the first step towards implemetation on FPGA of DTC-SVM. Future work will extend this experimental validation to the study.