Low Power CMOS Electrocardiogram Amplifier Design for Wearable Cardiac Screening

ABSTRACT


INTRODUCTION
Cardiovascular disease is the number one killer disease in Malaysia.Although sudden cardiac arrest is the main cause of death, the Malaysian awareness of towards cardiovascular disease is still low.Having threatened by the cardiovascular disease in among the middle age to old people is very worrying especially when these people are staying alone or have no relatives staying nearby to him or her.While sudden cardiac arrest is the main cause of death due to the sudden stop-functioning of the heart [1], the case is even worst when the patient is staying alone where nobody is aware of the patient's mortality.To reduce the risk of fatality, continuous monitoring of the electrocardiogram (ECG) signal and analyzing the heart rate variability (HRV) is desired in public community for early prevention as well as emergency treatment of serious heart diseases.Hence, it is important to make a complete cardiac screening system on chip (SoC) that is suitable to be used with the wearable devices and internet of things (IoT).
The trend and demand in the health care devices is increasing towards more portability and less patient mobility restriction as compared to the previous year, especially in this era where the emerging of IoT is very promising in near future.In the last few decades, the introduction of full system on a silicon chip (SoC) has introduced the world to the low power small size devices, which has been evolved to today's ultra low power wearable device.With the advancement of complementary metal oxide semiconductor (CMOS) technology, this SoC has enabled the implementation of biomedical signal acquisition and processing such that the cardiac signal monitoring.
The existing one lead ECG front-end amplifiers are very prone to noisy environment such as 50Hz powerline magnetic field interference, causing the signal is being interfered with the powerline noise [2]- [5].As the heart signal is a low frequency signal, flicker noise at low frequency is also very prominent in the circuit output.Large and unstable input offsets due to impedance between electrodes and skin causes the amplifier to be saturated easily.These noise and offset are not suitable to be used for wearable monitoring system implementation.[2], [4], [5].Therefore, a low noise and low power amplifier circuit is required for a future realization of a SoC ECG monitoring system.This paper proposed a front-end ECG amplifier by using a standard 0.13µm CMOS technology from Silterra with power supply of 1.2V.

CIRCUIT IMPLEMENTATION
ECG signal is a systematic electrical signal that is generated by the heart muscle to trigger the heart pumping activity or the cardiac cycle rhythmically and precisely.Typical cardiac signal strength is ranged between 5µV to 8mV while its frequency is ranged at 0.05Hz to 250Hz.This work focuses on designing a front-end CMOS amplifier circuit that is capable to detect this weak ECG signal while achieving low power and low noise circuit performance.Several considerations are counted into the amplifier design in order to eliminate the noise such as the transistor's threshold biasing and circuit approach to get highest common mode rejection ratio (CMRR).

Subthreshold biasing
Subthreshold biasing of the transistors can reduce the transistor noise and the power consumption as the minimum operating voltage can be achieved [6].In fact, it is getting more attention in biomedical amplifier research in recent times due to the ability to design ultra-low power sensors and amplifiers for low frequency applications [7], [8].Sub-threshold equation for transconductance in sub-threshold region is shown in Equation ( 1). ( Equation (1) shows that the transconductance of the transistor is linearly proportional to the biasing current I D rather than proportional to square root I D .Thus, lower current can be used to achieve the same amount of transconductance and gain of the amplifier leading to low power design.
Equation (2) shows the drain current of the transistor in subthreshold operation where I DO is the current when V = V T .The current is directly proportional to the aspect ratio of the transistor, as similar to the transistor operation in saturation region, shown in Equation (3). (3)

Design topology
Folded cascode operational amplifier was used as the input signal amplifier design topology.This is because folded cascode topology achieves single pole, stable phase margin, and higher swing while maintaining the same gain as the telescopic cascode amplifier topology [9].The folded cascode amplifier can also able to achieve low power consumption and low noise design [10], [11].PMOS transistor was used as the input transistors because it can achieve higher CMRR and lower flicker noise since the flicker noise is inversely proportional with the size of the transistor [12].
Figure 1 shows the proposed folded cascode operational amplifier with self-biasing circuit.This design uses PMOS amplifier as the input and the modified current mirror to eliminate the extra threshold voltage used in the headroom.The design parameters was started by allocating biasing current to the branches of the transistors.After that the minimum drain-to-source voltage or overdrive voltage of the transistors was set by using initial guess based on the allocated current to the branches.Higher overdrive voltage was given to M bs and M 5, 6 as they need to drive more current comparing to other transistors.Design performance optimization was done by repeatedly changing the sizing aspect ratio and the biasing current until the performance specification is met.Subthreshold transistor biasing was made possible as the cardiac signal frequency is low and the noise can be reduced.The transistors' aspect ratio were shown in Table 1.As can be seen from the table, the transistors sizing ratio especially near to the power supply and input section are larger to eliminate the flicker noise and increase the CMRR as much as possible.Larger input transistors size ratio is also contributing to a higher gain due to the transconductance g m is directly contributing to the gain of the amplifier.The biasing current is set to 250nA at the voltage supply, V DD of 1.2V.Finally, the designed transistor circuit was then encapsulated into an op-amp circuit with the instrumentation amplifier connection to test its functional and the performance such as gain, phase margin, CMRR, power supply rejection ratio (PSRR) and noise.

RESULTS AND DISCUSSION
All results are simulated using Cadence Electronics Design Automation (EDA) tools.Virtuoso Analog Design Environment L was used for circuit schematic design simulation works and Virtuoso Visualization & Analysis XL was used to plot the signal waveforms and measurements.

Transient response
The output transient waveform of the circuit is simulated to ensure that the amplifier is working when the input is low peak-to-peak voltage, V p-p and the swing is not saturated when the input is high V p-p .The simulated output swing of 1.018V p-p is observed when the input voltage is at maximum swing of 20mV p-p , meanwhile output swing of 0.6mV p-p is obtained when the input voltage maximum swing is at 10µV p-p .
From the simulation, it is found that the optimized circuit can succesfully response to different frequency and amplitude within the range from 0.05 Hz to 250 Hz and 5 µV to 10 mV respectively which means able to support the cardiac signal characteristics range.The DC biasing point is set at 0.6 V for maximum voltage swing.

AC response
The circuit ac response was simulated using the Middlebrook's method [13].This is because this method can achieve stable DC operating point and the loop gain can be obtained by directly calculating the voltage gain.Figure 2 shows the simulated ac response of the amplifier.The circuit can achieve gain of 75.45dB, phase margin of 80.9 o , unity gain bandwidth (GBW) of 667.5kHz, and -3dB frequency of 128.82Hz.The load capacitor of the amplifier is 1pF.

Circuit performance
The common mode rejection ratio (CMRR) of the circuit is defined as the ratio of the differential gain to the common mode gain and is calculated based on the following equation.

(4)
Here, A c is the common mode gain and A d is the differential gain of the circuit.The common mode gain simulation was obtained by injecting a common mode signal into both amplifier input and the output ac response is measured.The measured common mode gain is -98.65 dB and the resulting CMRR is 174.05dB.
Power supply rejection ratio (PSRR) of the amplifier is defined as a ratio of the variation of supply voltage to the amplifier to the variation of output voltage the amplifier produces.During simulation, a small sinusoidal voltage of 10mV was placed in series with the supply voltage and the ratio of the power supply variation to the output variation of the amplifier is measured.The obtained PSRR of the amplifier is found to be 92.12dB.
Input referred noise includes the thermal noise and flicker noise.However, the flicker noise is more concern due to the ECG is a low frequency signal.Flicker noise as shown in equation below is inversely proportional to the size of the transistor. (5) Here, K is the transistor flicker noise factor.Figure 3 shows the noise voltage model used to derive the input referred noise.The input referred noise for the circuit in Figure 1 can be expressed by the equation below.
( ) From Equation ( 6), K n and K p are the flicker noise coefficients for NMOS and PMOS, respectively.It is shown that the W/L ratio of the transistors P 9 , P 10 , N 5 , and N 6 are critical in reducing the flicker noise as the flicker noise is inversely proportional to the product of the W and L of the transistor and g m1, 2 of the input transistors.The L was kept minimum to ensure that the capacitance effect of the transistor is as less as possible.Figure 4 shows the input referred noise response of the circuit.The noise was set as a variable during the simulation.It is observed that the input response noise of the circuit is 1.01 √ .
Figure 4. Input referred noise response of designed circuit

Design performance comparison
The simulated response performance of the designed circuit has been compared with the previous related works.Table 2 summarizes the performance comparison between the proposed design and the previous work.This work has been shown to improve CMRR, PSRR and reduce the noise introduced to the front end amplifier system.√ .This amplifier design can achieve lower power consumption of 3µW which is comparable to previous works and also suitable to be implemented into a SoC design.

Figure 2 .
Figure 2. AC response of amplifier circuit.Upper graph shows the phase response and lower graph shows the gain response

Table 2 .
Perfomance Comparison and low noise with high CMRR and PSRR cardiac signal amplifier is presented to improve the noise issue known in a cardiac signal.The amplifier achieves gain of 75.4dB, phase margin of , CMRR of 174.05dB,PSRR of 92dB, and input referred noise of 1.01 Low Power CMOS Electrocardiogram Amplifier Design for Wearable Cardiac Screening (Ow Tze Weng) 1835 80 o