CCII and FPGA Realization: A Multistable Modified Fourth-Order Autonomous Chua’s Chaotic System with Coexisting Multiple Attractors

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Multistability is a critical property of nonlinear dynamical systems, where a variety of behaviors such as coexisting attractors can appear for the same parameters, but different initial conditions. e flexibility in the system's performance can be archived without changing parameters [64,65]. is has become a very popular research topic and some important research results have been achieved recently [11,[66][67][68][69]. In [66], a 4D memristor-based Colpitts system was proposed by employing an ideal memristor to substitute the exponential nonlinear term of original 3D Colpitts oscillator model, from which the initials-dependent extreme multistability was exhibited by phase portraits and local basins of attraction. In [67], an ideal voltage-controlled memristor emulator-based canonical Chua's circuit was investigated. With the voltage-current model, the initial condition-dependent extreme multistability was explored through analyzing the stability distribution of line equilibrium point and then the coexisting infinitely many attractors were numerically uncovered in such a memristive circuit by the attraction basin and phase portraits. In [69], a 5D multistable four-wing memristive hyperchaotic system (FWMHS) with linear equilibrium points was proposed by introducing a flux-controlled memristor model with absolute value function. A secure communication scheme based on the proposed 5D multistable FWMHS with disturbance inputs was also designed. To our best knowledge, fourthorder autonomous Chua's chaotic systems with multistability are rare in literature. erefore, it is of great significance to study a fourth-order Chua's chaotic system with multistability.
In recent years, there exist several studies related to fourth-order autonomous Chua's chaotic circuits [70][71][72][73]. e design of a new fourth-order autonomous nonlinear electric circuit using two active elements, one linear negative conductance, and one nonlinear resistor has been proposed by Koliopanos et al. to show rich dynamic behavior of Chua's circuit [71]. In the performed study by Liu et al., the design of fourth-order Chua's circuit has been proposed with a piecewise-linear nonlinearity and with a smooth cubic nonlinearity which could produce different kinds of attractors [72]. Wang et al. designed a fourth-order Chua's circuit using a capacitor, a resistance, and a controlledsource constituted by stair functions in the third-order Chua's circuit which could generate multidirectional multiscroll (MDMS) chaotic attractors [73]. However, the passive inductors are used in the circuits proposed in [70][71][72][73]. In fact, the parameters of passive inductor are not only difficult to control accurately in the actual Chua's circuit, but also very easy to be affected by frequency, environment, and other factors. Generally speaking, the internal resistance of the inductor will affect the oscillating circuit, and the larger the value of the inductor, the greater the internal resistance of the inductor, and the greater the impact on the circuit. In order to minimize the influence of the internal resistance of the inductor on the circuit, the actual inductor can be replaced by the active inductor in the experiment. e active inductor can be equivalent to the ideal inductor without internal resistance consumption [74,75].
Meanwhile, these modified Chua's circuits generally use ordinary voltage-mode operational amplifiers as active devices. Because the gain-bandwidth product of voltage-mode operational amplifiers is limited (usually several megahertz), it is necessary to balance the gain and bandwidth in the design of circuits. at is to say, in order to get a large circuit gain, the operating frequency of the circuit can only be reduced [76][77][78][79]. And the current-mode devices have good frequency gain characteristics. e bandwidth of these kind of devices is almost independent of gain, so there is no need to weigh the gain and bandwidth in the designed circuit, which can improve the working frequency of the circuit [80]. In recent years, the current-mode devices to realize Chua's circuit have gradually become a new research direction. In [81], active simulated inductor and piecewise nonlinear resistor in the circuit were all realized by second-generation current conveyors (CCIIs), so that the circuit was more stable and can work in higher frequency than does the usual Chua's circuit. e circuit also had the advantages in that the current waves and the corresponding phase diagrams could be tested easily. Jothimurugan et al. [82] reported an improved implementation of an inductorless third-order autonomous canonical Chua's circuit.
e active elements as well as the synthetic inductor employed in this circuit were designed using current feedback operational amplifiers (CFOAs). e implementation of inductorless makes the experimental construction of Chua's circuit simple and compact.
Many analog implementations of chaotic systems in electronic circuits have been reported in recent decades, such as the well-known breadboard with discrete components [10,13,27,28] and CMOS technology for integrated circuit (IC) design [12,23,24]. However, breadboard is not easy to carry, maintain, and store data, and IC design has a long cycle and high cost [83][84][85][86][87]. Meanwhile, in some chaotic information systems, digital implementation may be necessary, for example, in embedded chaos-based application areas and many other chaotic digital information systems. Digital chaotic generators have been implemented by varied structures such as Digital Signal Processor (DSP) [88,89] and Field Programmable Gate Array (FPGA) [90][91][92][93][94]. In order to calculate complex mathematical operations, the DSP chips are optimized operations sequentially. Constant-time autonomous chaotic systems are characterized by at least three differential equations and at least three outputs. erefore, it takes a long time for systems based on DSP to calculate the output signal values in turn. On the other hand, the FPGA chip can run in parallel and has a relatively flexible architecture. erefore, the design and test cycle cost of the FPGA chip is extremely low. Moreover, because of its reprogrammability, high speed, and large capacity, the implementation of FPGA is of great significance in the fields of information security, encryption, cryptography, communication, and other applications [95,96].

Complexity
In recent years, the design of chaotic system based on FPGA has been extensively studied. In [90], by the help of fourth-order of RK4 method, Sundarapandian-Pehlivan chaotic system was proposed in VHDL 32-bit IEEE 754-1985 floating-point number standard on Virtex-6 FPGA chip. In [91], autonomous Lu-Chen chaotic system was implemented on Virtex-6 FPGA chip using Heun numerical algorithm in VHDL 32-bit IQ-Math fixed-point number format. In [92], with the method of Artificial Neural Networks, the design of Pehlivan-Uyaroglu chaotic system was implemented in VHDL IEEE 754 single precision floating-point number format on Virtex-6 FPGA chip. A 3D nonequilibrium chaotic system using RK4 numerical algorithm with IEEE 754-1985 floating-point number standard on Virtex-6 FPGA chip was designed in [93]. In [94], the implementation of multibutterfly chaotic system in FPGA by applying the Xilinx (Vivado) system generator was proposed. e objective of this study is twofold. First, based on a multistable modified fourth-order autonomous Chua's chaotic circuit introduced in [70], an improved implementation of an inductorless modified fourth-order autonomous Chua's chaotic circuit is proposed. e active elements as well as the synthetic inductor employed in this circuit are designed using CCIIs. e reason for employing CCIIs is that, compared with circuits designed with voltage operational amplifiers, CCIIs have better characteristics such as high conversion rate and high working speed, so that the circuit can work in higher frequency ranges. Second, the RK-4 method in a hardware description language (VHDL) is used to model the modified fourth-order autonomous Chua's chaotic system, and the model is tested comprehensively on Xilinx Virtex-6 FPGA chip. e phase portraits of the output result of the system based on FPGA are given. e design results of the modified Chua's chaotic oscillator based on FPGA are compared with those of computer, which verifies the correctness of the design based on digital circuit. e structure of this paper is as follows: a multistable modified fourth-order autonomous Chua's chaotic system is investigated and the dynamic characteristics are discussed in Section 2. An inductorless modified fourth-order autonomous Chua's chaotic circuit is constructed by using CCII in Section 3.
e Multisim simulation results of the inductorless modified Chua's chaotic circuit are also given. In Section 4, the FPGA-based model of the modified fourthorder autonomous Chua's chaotic system is introduced and simulation results of FPGA-based model are presented. Finally, conclusions are outlined in Section 5.

Modified Fourth-Order Autonomous Chua's Chaotic
Circuit. By adding a linear resistor and a linear capacitor to the classical Chua's chaotic circuit, a modified fourth-order autonomous Chua's chaotic circuit is introduced in [70], as shown in Figure 1. According to Kirchhoff's law, the dynamics of this circuit is governed by the following equations: , and i L are state variables which denote the voltage across C 1 , the voltage across C 2 , the voltage across C 3 , and current through L, respectively. According to the principle of Chua's diode in classical Chua's chaotic circuit, the characteristic curve of Chua's diode NR in (1) can be graphically represented as in Figure 2 and is given by where G a and G b are the slopes of the outer and inner regions, respectively, and ± E a denote the breakpoints.

System Generation and Dynamics Analysis.
When the parameters are selected as C 1 � 10 nF, C 2 � 100 nF, L � 17.64 mH, R � 1.68 kΩ, C 3 � 2 μF, E a � 1, G a � −1.28 ms, G b � −0.69 ms, and R 0 � 60 Ω, we can get α � 10, attractor is generated by MATLAB simulation under the initial condition [0, 0.1, 0, 0], as shown in Figure 3. As can be seen from Figure 3, when the parameters of the system satisfy certain conditions, a self-excited oscillation attractor called double-scroll, like Chua's circuit, will also be generated. Chaotic orbits are currents circling around strange attractors [59]. e nonperiodicity of chaotic oscillation can be clearly seen from the time-domain waveforms, as shown in Figure 4. e dynamic system described by differential equation (3) is symmetric with respect to origin and corresponds to the characteristics of Chua's diode NR. If the characteristics of Chua's diode NR are divided into three sections; that is, e three subspaces in the state space of (4) are ere are unique equilibrium points in three subspaces of the state space. e three unique equilibrium points are Linearization is carried out at the equilibrium point Q(0, 0, 0, 0), and the linearization matrix is obtained as follows: Four eigenvalues of the above matrix can be calculated: 3.9298, −1.0103 + 3.3587i, −1.0103 − 3.3587i, and −1.5092, linearized at equilibrium points P + and P − , and the linearized matrix can be obtained as follows: Four eigenvalues of the above matrix are calculated: −4.5531, 0.1295 + 3.4095i, 0.1295 − 3.4095i, −1.2060. erefore, all equilibrium points P + , Q, and P − are saddle points. In the macroscopic view of chaotic attractors, holes are formed near P + and P − , respectively, which are like two whirlpools twisted together, showing a double-scroll chaotic strange attractor (Figure 3). is is the result of the combination of global stability and local instability. Chaotic orbits are the flow whirling around the strange attractor. e adjacent trajectories show a tendency of mutual exclusion and separation at an exponential rate [70].
ere are many interesting chaotic phenomena when the system parameters are changed continuously. However, in order to debug the experimental circuit conveniently in the future, only the resistance R is changed to observe the x − y plane at the ends of C 1 and C 2 . In the simulation process, the x − y plane at the ends of C 1 and C 2 also shows that period-1 limit cycle, period-2 limit cycle, period-4 limit cycle, and single-band chaotic attractor are shown in Figure 5 and Table 1. It can be seen that the modified Chua's chaotic circuit exhibits abundant dynamic behavior of period doubling bifurcation sequence.

Multistability Analysis.
Multistability allows flexibility of system performance without changing parameters, and appropriate control strategies can be used to induce switching behavior between different coexisting states. In order to study the complex dynamic characteristics of the system better, it is necessary to give some disturbance to the initial conditions, that is, to change the initial conditions of the system under the condition of keeping the system parameters unchanged. Figure 6 shows the coexistence phenomenon of the system under two different initial conditions. e initial condition of the blue trace is 0, 0.1, 0, 0 and the initial condition of the red trace is 0, −0.1, 0, 0 . It can be seen from Figure 6 that, under these two initial conditions, the attractors exhibited by the system are exactly the same, but the directions of the trajectories are different, which all depend on the symmetry of the system. Figure 6 shows the coexistence attractors for different parameter values β and c 1 . Figure 6(a) shows that the system has coexisting double-scroll chaotic attractors. Figure 6(b) shows that the system has coexisting single band chaotic attractors. Figure 6(c) shows that the system shows coexisting period-4 limit cycle. It is very interesting that Figure 6(d) shows that the system has a period-2 limit cycle coexistence phenomenon. Figure 6(e) shows that the system has a period-1 limit cycle coexistence phenomenon. Figure 6(f ) is a time-domain waveform diagram of state x, and its parameter values are the same as period-1 limit cycle.

Inductorless Modified Chua's Chaotic Circuit Realized by CCII.
Current conveyor is a kind of electronic device with good high frequency performance, strong versatility, and flexibility, which has attracted wide attention of scholars [76][77][78][79][80][81]. In this part, a modified Chua's chaotic circuit realized by current conveyor is proposed. e key is to realize piecewise linear resistance NR and inductance L in Chua's chaotic circuit by using CCII commercial chip AD844 (current feedback operational amplifier) as the basic active device.
3.1.1. CCII. CCII is one of the most commonly used active devices in current-mode circuits. e symbolic representation of CCII is shown in Figure 7. Port relationship of CCII is where V X and I X are the voltage and current of X-terminal, V Y and I Y are the voltage and current of Y-terminal, and V Z and I Z are the voltage and current of Z-terminal, respectively. K is the transmission coefficient of the current conveyor. When K � 1, it is the in-phase current conveyor, and when K � −1, it is the reverse-phase current conveyor. e in-phase current conveyor can be implemented with one AD844, while the reverse-phase current conveyor needs two AD844.
e implementation circuits are shown in Figures 8(a) and 8(b), respectively.

Five-Segment Piecewise Nonlinear Resistance (NR).
Generally, when we use CCII to construct a nonlinear functional circuit, the five-segment piecewise nonlinear    Figure 7: Symbolic representation of CCII. resistance is employed. As shown in Figure 2, the input voltage is given to make it work in the middle of three BCDE segments. A five-piece nonlinear resistance [81] can be formed by parallel connection of two CCIIs, as shown in Figure 9(a). In Figure 2, the five-segment piecewise nonlinear resistance (NR) V-I characteristic curve ABCDEF is generated by the circuit structure, the BCDE section has the characteristics of nonlinear negative resistance, and Chua's chaotic circuit mainly works in this curve section. e turning voltage and slope of the two circuits are E a , E b , G a , and G b , respectively. erefore, the V-I characteristic curve of the five-segment piecewise nonlinear resistance can be obtained as follows: According to the structure characteristics of the circuit shown in Figure 2, the slope expressions of each section are as follows: e turning voltages of the circuit are where V CC is the power supply voltage of the amplifier. Figure 9(b) shows the five-segment piecewise nonlinear resistance V-I characteristic curve of Figure 9(a)'s circuit which is simulated by Multisim. It can be seen that the curve is completely consistent with the performance of Figure 2.

Lossless Grounded Active Inductor (L eq ).
Although inductor is an important passive device in IC design, it is not easy to integrate because it cannot integrate itself. erefore, spiral inductors are widely used in integrated circuits. Even so, there are some disadvantages, such as low adjustability, weight, large area, and high cost [82]. erefore, in order to overcome these difficulties, inductance simulators are used as substitutes for spiral inductors in many circuit applications [97]. In this study, a lossless grounded active inductor based on CCII developed by Yang is used [81]. is is because CCII has proven to be very useful in either current or voltage-mode signal processing circuits. e principle circuit of the lossless grounded active inductor realized by CCII is shown in Figure 10.
In Figure 10, CCII-, Z 1 , and Z 2 form a voltage amplifier. CCII+, Z 2 , and Z 3 form a current amplifier. e input voltage v i is added to the Y-terminal of CCII-and amplified by the voltage amplifier composed of CCII-, Z 1 , and Z 2 . According to the voltage-current relationship of CCII, if K � 1, the equivalent input impedance of the circuit shown in Figure 9(a) is It can be seen that the circuit shown in Figure 10 is an impedance converter, which can realize impedance conversion. By changing the properties of impedance Z 1 , Z 2 , and Z 3 , different equivalent impedance can be obtained. If Z 1 � R 1 , Z 2 � R 2 , and Z 3 � 1/SC, the circuit can realize a lossless grounded active inductor, and the equivalent inductance value of the lossless grounded active inductor is

Inductorless Modified Fourth-Order Autonomous
Chua's Chaotic Circuit. Figure 11 shows the modified Chua's chaotic circuit designed using CCII. e upper part inside the dash box of the circuit simulates a grounded inductor (L eq ), the right part inside the dash box is piecewise five-segment linear NR designed using CCII, and the left Figure 8: Implementation of the in-phase current conveyor (a) and the reverse-phase current conveyor (b).

Complexity 7
part inside the dash box of the circuit is a linear RC network. e inspection of the present circuit configuration reveals that all the four state variables V C1 , V C2 , i L , and V C3 , as stated in (1), are available from the circuit. e simulated inductance L eq is composed of one CCII+, two CCIIs-, and one capacitor C 4 . RC network is composed of C 1 , C 2 , C 3 , R 0 , and R. C 2 , C 3 , and L eq constitute resonant circuit. C 1 and piecewise linear resistance circuit are connected in parallel. Resistor R connects linear circuit and nonlinear circuit to form chaotic circuit. e values of components are taken in Table 2. is circuit is biased with ±15 V supply. A doublescroll attractor is observed for R � 1680 Ω as shown in Figure 12. rough the simulation of the circuit, we have also observed a variety of dynamic behaviors, such as single band chain attractor, period-4 limit cycle, period-2 limit cycle, period-1 limit cycle, steady state, and limit cycle, as shown in Figure 13. It can be seen that the Multisim simulation results are in good agreement with the theoretical analysis, which verifies the feasibility of the modified Chua's circuit.

FPGA Implementation of the Multistable Modified Fourth-Order Autonomous Chua's Chaotic System
e multistable modified fourth-order autonomous Chua's chaotic system presented in this study is modeled on Lab-VIEW FPGA using Runge-Kutta (RK-4) algorithm, which is one of the most popular numerical differential equation decryption methods in the literature. According to the 32-bit IEEE 754-1985 floating-point number standard, the design is coded on VHDL (Very-High-Speed High Speed Integrated Circuit Hardware Description Language) [98]. IP core generator developed by Vivado 2018.3 Design Tools system is used to design chaotic oscillator based on FPGA, such as multiplier, subtractor, and adder, which conform to IEEE 754-1985 standard.

RK-4 Algorithm.
Runge-Kutta (RK) algorithm is a high precision one-step algorithm widely used in engineering. e theoretical basis of the algorithm is derived from Taylor's formula and the slope approximation to express the differential. It predicts the slope of several points several times in the integral interval, then carries out weighted averaging, which is used as the basis for the next point, and thus constructs a numerical integration calculation method with higher accuracy [90]. If the slopes of four points are calculated beforehand, it is the fourth-order Runge-Kutta (RK-4) algorithm. For differential equation _ y � f(x, y), the theoretical formula of RK-4 is as follows: where K1, K2, K3, K4 denote the first-order reciprocal of the output variable, that is, the differential at a point, expressed as the slope. e iteration step is Δh � 0.001. Figure 14 shows the block diagram of Chua's oscillator using RK-4 algorithm.
x 0 , y 0 , z 0 , and w 0 signals are the initial conditions (IC) for the system to start running. In the design, they are defined as 32-bit symbolic floating-point numbers, which are determined internally by the user. e purpose of the multiplexer unit (MUX) is to select the external initial conditions at the  Figure 9: Five-segment piecewise nonlinear resistance implemented by two CCIIs: (a) circuit structure and (b) V-I characteristic simulated by Multisim.
8 Complexity start or the internal values provided by the RK4-based oscillator unit in the successive steps. In the continuous steps after the start of operation, the x k+1 , y k+1 , z k+1 , and w k+1 signals generated by the oscillator unit are used as feedback inputs of the multiplexing unit, that is, the input signals of the next step, such as x k , y k , z k , and w k . e oscillator unit consists of six modules : K1, K2, K3, K4, ys, and

FPGA Implementation.
e top level block diagram of the modified fourth-order Chua's oscillator based on FPGA designed by RK-4 algorithm is shown in Figure 15. As can be seen from Figure 15, the design system has three inputs and five outputs. e input signal consists of a 1-bit clock signal (Clk), a 1-bit Reset, and a 32-bit Δh. Clk and Reset are used to ensure synchronization between the system and other modules. 32-bit Δh represents the step size, which is used to determine the sensitivity of the algorithm. e output signal consists of four 32-bit output signals X out, Y out, Z out, W out and 1-bit flag signal XYZW ready. When the calculation generates X out, Y out, Z out, W out, the flag signal XYZW ready is output. e second level block diagram is composed of modified Chua's chaotic oscillator, floating-point to fixed-point unit, and digital-to-analog converter, as shown in Figure 16. e oscillator unit has three input signals, 1-bit Run, 1-bit ,Clk and 32-bit Δh, respectively. e 1-bit XYZW ready data signal provides the clock signal for the DAC unit. At the output of chaotic oscillator based on Rk-4, there are four floating-point standard 32-bit output signals (X out, Y out, Z out, W out). ese signals are equivalent to the x, y, z, and w variables of the continuous-time chaotic system (3).  Figure 11: Inductorless modified Chua's chaotic circuit realized by CCII. 220 Ω R 2 220 kΩ R 3 220 Ω R 4 2.2 kΩ R 5 22 kΩ R 6 220 kΩ R 7 22 kΩ R 8 3.3k Ω R 9 1 kΩ R 10 220 kΩ R 11 1 kΩ R 12 220 kΩ R 13 220 kΩ R Variable C 1 10 nF C 2 100 nF C 3 2 μF C 4 17.64 nF e input of the floating-point to fixed-point unit is four 32bit output signals of the oscillator unit, which converts the output of the former unit into 14-bit unsigned fixed-point. e DAC module converts the digital signal generated by the chaotic system into analog signal and outputs it to the oscilloscope. In the actual experiment, we choose X out, Y out, and Z out to output the dual-channel DAC module and then the oscilloscope.

FPGA Test Results.
e modified multistable fourthorder Chua's chaotic system based on RK-4 is synthesized on

Complexity
Xilinx ZYNQ-XC7Z020 chip. e use of the chip source and the clock speed of the system are calculated. Using Vivado 2018.3 design tool, the data processing duration of the modified fourth-order Chua's chaotic system designed in this paper is determined. e X Out, Y Out, Z Out, and W Out signals are equivalent to the x, y, z, and w signals in the system. Although the 32-bit floating-point standard is adopted in the system design, which makes it easier to detect the time series values of these signals, the Vivado simulation results are displayed in hexadecimal digital format. e results of the Xilinx ISim simulator for the modified fourth-order Chua's chaotic system are shown in Figure 17 when Δh � 0.001. e system runs in pipeline mode and produces x, y, z, and w signals after every 320 clock cycles. Figure 18 shows the power utilized by the system. Table 3 shows the resources utilized by the chaotic oscillator implemented on FPGA including the clock frequency.
e minimum working period of the modified fourth-order Chua's chaotic system signal generator based on FPGA is 5.55 ns. Finally, the X Out, Y Out, and Z Out signals obtained from the RK4-based FPGA design of the system are recorded in a file in the form of 32-bit floatingpoint hexadecimal number during the test step, which is given in Table 4. e phase portraits of the output signals are obtained using the data set generated in decimal format by the modified fourth-order Chua's chaotic system based on FPGA given in Table 4. Two pictures of the double-scroll chaotic attractors and single band chaotic attractor and period limit cycles obtained from the hardware implementation of the RK4-based modified fourthorder Chua's chaotic system on FPGA are shown in Figures 19 and 20, respectively. e results show that the phase portraits obtained by the model based on MATLAB and FPGA have good consistency. Although the implementation of FPGA has a reputation of being difficult to design, with the help of system methodology, the system can require less work than the traditional software-based implementation [99,100].    Figure 19: Implementation platform and exemplification of the double-scroll chaotic attractors generated by the FPGA implementation of the multistable modified fourth-order Chua's chaotic system. Figure 20: Implementation platform and exemplification of the single band chaotic attractor and period limit cycles generated by the FPGA implementation of the multistable modified fourth-order Chua's chaotic system.

Conclusion
A multistable modified fourth-order autonomous Chua's chaotic system is first investigated. en the modified implementation of fourth-order autonomous Chua's chaotic circuit with CCII based active elements and synthetic inductor is reported. Synthetic inductor instead of the inductor coil makes the circuit more suitable for the fabrication of integrated circuits, which can be used for the study of coupled dynamics and spatiotemporal chaos. e modified Chua's circuit exhibits abundant dynamic behavior of period doubling bifurcation sequence. Finally, the design of multistable modified fourth-order autonomous Chua's chaotic system based on discrete-time FPGA is implemented on Xilinx Virtex-6 (ZYNQ-XC7Z020) chip using RK-4 algorithm. e maximum operating frequency of the designed chaotic system reaches 180.180 MHz. As can be observed from the results, the chaotic signal generator based on FPGA proposed in this paper can be used as a good entropy source in the applications of secure communication, cryptosystem, and random number generator.

Data Availability
All data used to support the findings of this study are available from the corresponding authors upon request.

Conflicts of Interest
e authors declare that they have no conflicts of interest.