A Low-Power Ultrawideband Low-Noise Amplifier in 0.18 μm CMOS Technology

This paper presents an ultrawideband low-noise amplifier chip using TSMC 0.18μm CMOS technology. We propose a UWB low noise amplifier (LNA) for low-voltage and low-power application. The present UWB LNA leads to a better performance in terms of isolation, chip size, and power consumption for low supply voltage. This UWB LNA is designed based on a current-reused topology, and a simplified RLC circuit is used to achieve the input broadband matching. Output impedance introduces the LC matching method to reduce power consumption. The measured results of the proposed LNA show an average power gain (S 21 ) of 9 dB with the 3 dB band from 3 to 5.6GHz. The input reflection coefficient (S 11 ) less than −9 dB is from 3 to 11 GHz. The output reflection coefficient (S 22 ) less than −8 dB is from 3 to 7.5 GHz. The noise figure 4.6–5.3 dB is from 3 to 5.6GHz. Input third-orderintercept point (IIP 3 ) of 2 dBm is at 5.3 GHz. The dc power consumption of this LNA is 9mW under the supply of a 1 V supply voltage. The chip size of the CMOS UWB LNA is 1.03 × 0.78mm in total.


Introduction
The ultrawideband (UWB) system has become one of the major technologies for wireless communication systems and local area networks. The IEEE 802. 15.3a ultrawideband (UWB) system uses a specific frequency band (3.1 GHz∼ 10.6 GHz) to access data and employs the system of orthogonal frequency-division multiplexing (OFDM) modulation [1][2][3]. The frequency band consists of four groups: A, B, C, and D, with thirteen channels. Each channel bandwidth is 528 MHz, as shown in Figure 1. The system operates across a wide range of frequency 3.1-5 GHz or 3.1-10.6 GHz. The low frequency band from 3.1 to 5 GHz has been allocated for developing the first generation of UWB systems [4]. The system has several advantages such as low complexity, low cost, and a high data rate for the wireless system. In the front-end system design, a low-noise amplifier (LNA) is the first block in the receiver path of a communication system. The chief objective of the LNA is to reach the low-noise figure to improve the overall system noise [5]. The LNA must minimize the noise figure over the entire bandwidth, feature flat gain, good linearity, wideband input-output matching, and low power consumption. In the radio frequency circuit design, GaAs and bipolar transistors have performed fairly well. Nevertheless, these processes lead to increased cost and greater complexity. The RF front-end circuits using CMOS technology can provide a single-chip solution, which greatly reduces the cost [6]. With the rapid improvement of CMOS technology, it can implement RF ICs with CMOS. Three major topologies of the present wideband low-noise amplifiers are used. First, distributed amplifiers [7][8][9] can provide good linearity and wideband matching but require high power consumption and a large chip area because of the multiple amplifying stages. Second, resistive shunt feedback amplifiers [4,10] provide good wideband matching and flat gain but require high power consumption. Last, Chebyshev filter amplifiers [11,12] adopt a wideband LC bandpass filter for input matching and a source follower for output matching. This type of wideband amplifier dissipates a small amount of dc power. The Chebyshev filter matching design requires three inductors. Therefore, a very large chip area is required. This paper proposes RLC broadband matching for LNA design. The primary goal is to obtain wideband input-output matching and to reduce the chip area and power consumption. The LNA topology is proposed in Section 2. The complete analysis of the design methodology of the wideband matching network is presented in Section 3. In Section 4, implementation and measurement results are presented. The conclusion is presented in the last section.

Low-Voltage Wideband
Cascode LNA Design Figure 2 shows the basic cascode LNA. The current-reused configuration can be considered as two common-source amplifiers ( 1 and 2 ). The current shared cascode amplifier provides a low-power characteristic under the low voltage supply. Because 1 and 2 share the same bias current, the total power consumption is minimized [6,12,16]. For a cascode amplifier, the overall noise figure can be obtained in terms of the noise figure (NF) and gain of each stage as follows: where total is the total NF and 1 and 2 are the NF values of the first and second stage; respectively. 1 is the power gain of this first stage, therefore, in the LNA circuits, the noise of the first stage is more critical. Consequently, the gain of the transistor's 1 must be high enough to suppress the noise.
The dominant noise sources for active MOSFET transistors are flicker and thermal noises. The flicker noise is modeled as the voltage source in series with the gate of value: where the constant is dependent on device characteristics and can vary widely for different devices in the same process. The variables , , and represent the width, length, and gate capacitance per unit area, respectively. The flicker noise is inversely proportional to the transistor area, . In other words, a larger device reduces this noise. The noise process of thermal noise is random. The MOSFET thermal noise includes three main noise sources, as shown in Figure 3: distributed gate resistance noise ( 2 rg ), drain current noise ( 2 nd ), and gate current noise ( 2 nd ). The thermal noise source mainly comes from the drain current noise and gate-induced noise of the transistors. Multifinger layout technology is applied to reduce the gateinduced noise. According to the MOSFET noise analysis in [17,18], we must express the noise figure in a way that explicitly considers power consumption. In order to determine the width of 1 and find out the best NF, we use the dependency among noise factor ( ), power dissipation (PD), and quality factor ( ) to find out the optimal value [17]. Based on these parameters, the related curves, NF (dB) versus , are plotted in Figure 4 by MATLAB simulation software. There is a compromise between noise performance and power gain in Figure 4. Therefore, the can be determined to be 4, as PD equals to 10 mW. The optimal width of MOSFET can be obtained by [17,18]: where is the operation frequency, is the gate length, and ox is the gate capacitance per unit area. Equation (3) shows that the optimal width for 1 is 240 m, for o = 3.4 GHz, = 0.18 m, = 8.62 F/m 2 , = 50Ω, and = 4. Figure 5 shows the proposed UWB LNA schematic. The current sharing cascode amplifier provides low-power characteristics with low voltage supply. Note that 2 is the common-gate stage of the cascode configuration, which eliminates the Miller effect and provides better isolation from the output return signal [18,19]. The passive components 1 , 2 , 3 , 1 , and 1 are adopted for the matching network at the input to resonate over the entire frequency band. The resistors 2 and are used to provide bias voltage for the transistors 1 and 2 . The capacitor 4 provides signal coupling between the two stages. The capacitor 5 bypasses the ac current to the ground and avoids coupling to the first stage. This affects gain flatness; therefore, it is possible to provide an ideal ac ground, but gain flatness is not affected in the design. 2 is the inductor load of the first stage. The output matching network is composed of 3 , 4 , 6 , and 7 . In the cascode stages, the first stage's noise figure contribution is more than the second stage's. The first stage's transistor size and bias point should be optimized for the low NF [17]. The second stage's transistor size and bias point should be optimized for high linearity. The cascode LNA design is full of trade-offs between optimal gain, low noise figure, input and output matching, linearity, and power consumption. Moreover, to avoid oscillation, the parasitic couplings have to be minimized [16]. The sizes of the devices of the LNA are shown in Table 1.

Proposed Wideband Matching Network Analysis
3.1. Input Impedance Matching. As shown in Figure 2, in the conventional narrow band LNA design, the input impedance of the input stage ( 1 ) can be written as where gs1 is the gate-source capacitance and 1 is the transconductance of the input transistor 1 . We choose appropriate values of inductance ( + ) and capacitance gs1 , which resonate at a certain frequency. The real term can be made equal to 50 Ω. Equation (3) determines the width of 1 and finds the best NF. For wideband design, it is difficult to let the imaginary part of (4) remain zero for a wide range. To discuss UWB input impedance matching, we need to consider the standard form of the second-order filter:      where 2 , 1 , and are numerator coefficients determining the type of second-order filter function. is called the pole frequency, in is termed the pole factor, and is called bandwidth. According to = / in , the bandwidth is inversely proportional to the in if the value of the pole frequency is fixed.   Active and Passive Electronic Components Figure 6: The proposed wideband matchingapproximate first stage input matching small-signal equivalent circuit. Figure 6 shows the proposed wideband matching and a small-signal equivalent circuit in the first stage. The input impedance of the RLC network can be written as Because 3 capacitance value is much larger than gs ( 3 ≫ gs ), the where gs1 is the gate-source capacitance of 1 . This equivalent circuit can roughly be an RLC second-order filter structure. In (7), the quality factor of the filter circuit can be given by where is the resonant frequency. In (8) and (9), to obtain broader bandwidth, a low-quality factor needs to be added to the passive devices. The narrowband LNA can be converted into a wideband amplifier by properly selecting passive devices. According to (8), the capacitors 2 , 3 and inductor 1 will be optimized at the resonant frequency. We use the CAD of Agilent ADS to analyze the circuit performance of input impedance matching. According to (8) and (9), is inversely proportional to 1 while is proportional to 1 . Therefore, bandwidth is inversely proportional to 1 . Figure 7 is fixed as 1 (9.51 pF), 2 (0.11 pF), 3 (7.6 pF), and 1 (140 Ω), showing that the resonant frequency is inversely proportional to the 1 . Bandwidth is inversely proportional to 1 . According to (9), the input matching circuit uses 1 and 3 to reduce the number of inductors and make the factor smaller. is inversely proportional to 1 . Therefore, bandwidth is proportional to 1 . Figure 8 is fixed as 1 (9.51 pF), 2 (0.11 pF), 3 (7.6 pF), and 1 (0.91 nH), showing that the bandwidth is proportional to the 1 . Figure 9 is fixed as 1 (9.51 pF), 2 (0.11 pF), 3 (7.6 pF), and 1 (0.91 nH), showing that the noise figure is inversely proportional to the 1 . is inversely proportional to 3 while is inversely proportional to 3 . Therefore, the bandwidth is proportional to the 3 . Figures 10 and 11 are fixed as 1 (9.51 pF), 2 (0.11 pF), 1 (140 Ω), and 1 (0.91 nH), showing that the bandwidth and noise figure are proportional to the 3 . The size of the transistors 1 , 1 , and 3 must be carefully selected. There is a trade-off in the design between wideband matching and the noise figure. On the other hand, the device size must yield a sufficient noise performance and power gain. As can be seen, the second-order filter of 1 (0.91 nH), 1 (140 Ω), and 3 (7.6 pF) is employed as the input matching network. The input matching network has less complexity and better reflection coefficient from 3 GHz to 10 GHz.

Output Impedance Matching.
Low-noise amplifiers rely on output impedance matching to achieve maximum power gain. A source follower technique has been widely used to provide wideband output matching. Output impedance is similar to 1/ , in which is a gate-source transconductance of the source follower [4,10]. However, it consumes more power. For these reasons, we introduce an output impedance matching method suitable for wideband LNA design. Figure 12 shows the approximate output impedance small-signal equivalent circuit. The output impedance of the RLC network can be written as out ≈ ( +(1/ 2 2 )) (( 7 + 6 ) / 6 7 ) 2 + (1/ 2 2 )+(( 6 4 + 6 3 + 2 3 ) / 2 6 3 4 ) , where 2 is the parasitic capacitance of 2 at the drain node, and 2 is the resistor of 2 at the drain node. This equivalent circuit can approximately be an RLC second-order   filter structure. In (11), the quality factor of the filter circuit can be given by ≈ 2 2 √ 6 4 + 6 3 + 2 3 where is the resonant frequency. In (12) and (13), in order to obtain broader bandwidth, a low-quality factor needs to be added to passive devices. is inversely proportional to R s = 50 Ω out Z C 7 L 4 C 6 L 3 r d2 C d2 Figure 12: The wideband output matching small-signal equivalent circuit. (3.1-5 GHz or 3.1-10.6 GHz) to access data. Generally the results of UWB return loss are less than −10 dB. The power consumption is proportional to the width of the transistor. According to (13), the narrowband LNA can be converted into a wideband amplifier by properly selecting 2 . This provides good wideband matching and flat gain. Figure 13 is fixed as 6 (0.16 pF), 7 (1.23 pF), 3 (1.19 nH), and 4 (0.59 nH), showing that the simulated 2 variation output reflection coefficient. As can be seen, the second-order filter of 2 (240/0.18 m) is employed as the output matching network. According to (12), the capacitor 6 and inductor 3 -4 will be optimized at the resonant frequency. Figure 14 is fixed as 6 (0.16 pF), 7 (1.23 pF), 2 (240/0.18 m), and 4 (0.59 nH), showing that the resonant frequency is inversely proportional to the 3 . The output network has less complexity and a better reflected coefficient from 3.1 GHz to 10.6 GHz.

Gain.
At a high frequency, the current gain of common source configured transistor 1 is 1 / gs1 [11]. Figure 15 shows the approximate first stage 1 load of the simplified  small-signal equivalent circuit [12]. The first stage load can be approximated as The transfer function of the input matching network is in ( ). The first stage voltage gain can be approximated as where is the source resistance, in which voltage gain is determined by the load inductor 2 , the total capacitance at the drain of 1 , and bypass capacitor 5 . The second stage voltage gain can be estimated as where in2 is the input resistance at the gate of 2 and out is the output load impedance. The LNA voltage gain can be approximated as According to (17), the narrowband LNA can be converted into a wideband amplifier by properly selecting the device size. This provides good wideband matching, noise figure optimization design, and flat gain.

Stability.
Amplifier stability is important to prevent natural oscillation. The stability can be determined by theparameters, input and output matching network, and circuit terminations. The simpler tests show whether or not a device can be unconditionally stable [20]. One of these is the -Δ test, which shows if a device can be unconditionally stable if Rollet's condition is defined as The -Δ test cannot be used to compare the relative stability of two or more devices because it involves constraints on two separate parameters. A new criterion has been proposed which combines the -parameters in a test involving only a single parameter, , defined as The performance of LNA is simulated using the advance design system (ADS). To consider the stability of the LNA, the factor and Δ should be considered. Figure 16 shows that the factor is always larger than 1 and the Δ is smaller than 1 all the time. Hence, this circuit is stable for all frequency bands. There is another way to diagnose whether the LNA is unconditionally stable. The factor at input and output should be larger than 1 in all frequency bands, as shown in Figure 17.

Measurement Results
On-wafer measurement is performed by an HP 8510C network analyzer and an HP 8517B is to test the -parameter, as shown in Figure 18. A network analyzer is used to measure the frequency response and input matching of the LNA. The input and output impedance matchings are both 50 Ω.
To ensure that the LNA still provides a conversion gain when process deviation occurs, the other process corners, namely, typical-NMOS typical-PMOS (TT), fast-NMOS fast-PMOS (FF), and slow-NMOS slow-PMOS (SS), are also used to simulate this LNA. The results are shown in Figure 19. Figure 19 shows the measurement forward gain ( 21 ), from 3 to 5.6 GHz; the measured gain is about 7-10 dB. The measurement data is 6 dB lower than the pre-simulation data because of the process drift and parasitic effect in the layout. The result of conversion gain measurement is situated in the post-simulation (SS) process corner. Figure 20 shows the input return loss (S 11 ), from 3 to 11 GHz, and the measured S 11 is less than −9 dB. Figure 21 shows output return loss (S 22 ), from 3 to 7.5 GHz, and the measured S 22 is less than −8 dB. Figure 22 shows reverse isolation (S 12 ), from 3 to 11 GHz, and the measured S 12 is less than −40 dB. The simulation measured input of 1 dB compression point at 5.3 GHz shown in Figure 23 is about −8 dB. Figure 24 shows the measured fundamental output power and thirdorder intermodulation (IM3) for the RF input frequency spacing of 1 MHz, and the IIP 3 is 2 dBm at 5.3 GHz. The IM3 is measured, using two Agilnet E8247C continuous wave   (CW) generators and an Agilent E4407B spectrum analyzer. A noise figure (NF) is measured, using an Agilent N8975A NF meter with an Agilent 346C noise source. The simulation noise figure minimum is 4.1 dB, as shown in Figure 25. Due to the parasitic effect in the layout, the minimum of the measurement is 4.6 dB. Figure 26 shows the micrograph of the LNA. Table 2 summarizes the measurement results and compares them with previous literature. In the proposed LNA topology, the simplified RLC input matching network and the current-reused configuration benefit from the lowpower design. The distributed amplifier [7][8][9] requires high power consumption and a large chip area. Compared with the Chebyshev filter and feedback network synthesis [11][12][13], the proposed input matching network, which has only one spiral inductor, simplifies the circuit complexity and  reduces the chip area. References [10][11][12] only show core LNA power consumption, excluding the output source follower. References [14,15] only show simulation. It should show the linearity of the experiment. The LNA plays an important role in improving overall system linearity. Table 2 clearly shows that the proposed LNA has a very small chip area and the lowest power consumption.

Conclusion
An RLC wideband matching UWB LNA has been presented in the above results, which can operate at a supply of 1 V voltage in a 0.18 m CMOS technology. In the proposed topology, the narrowband LNA can be converted into a wideband amplifier by the RLC matching method. The RLC input matching circuit reduces the chip area. The output matching method reduces power consumption. The main advantages of the LNA topology are low power use, moderate noise, linearity, power gain, and a small chip area.