Abstract
As CMOS transistors are scaled down beyond N10, the metal/semiconductor contact resistance becomes a dominant contributor to the total parasitic resistance of the FinFET or Nanowire FET. The utilization of highly-P doped Si:P for the selective source/drain epitaxy was previously shown to be a key enabler to achieve a low contact resistivity in combination with a Ti silicide direct contact and Ge pre-amorphization1.
In this paper, we report on the microscopic properties of strained Si:P epitaxial layers with P concentrations up to ~ 4.6 %. We discuss the details of the microstructure and the manifestation of Phosphorus-Vacancy complexes at high Phosphorus concentrations. We analyze how a post-epi thermal budget like spike or laser annealing is modifying the microstructure and leads to an enhanced P activation and diffusion.
In a second part, we zoom in on the different integration aspects of the Si:P layer for advanced bulk finFETs with a sub 10nm fin width and 45nm fin pitch. We discuss the role of the different epi parameters and the benefit of the high-P concentration for the final device performance2.
Acknowledgements
The imec core CMOS program members, European commission, local authorities and imec pilot line are acknowledged for their support.
References
[1] H. Yu et al., 2015 Technical Digest – International Electron Devices Meeting, 2015, Vol. 21.7, p. 592.
[2] T. Chiarella et al., submitted to ESSDERC 2016
Figure 1