Process Conditions for Low Interface State Density in Si-passivated Ge Devices with TmSiO Interfacial Layer

In this work we study the epitaxial Si growth with Si 2 H 6 for Ge surface passivation in CMOS devices. The Si-caps are grown on Ge in the hydrogen desorption limited regime at a nominal temperature of 400 °C. We evaluate the process window for the interface state density and show that there is an optimal Si-cap thickness between 8 and 9 monolayers for D it <5·10 11 cm -2 eV -1 . Moreover, we discuss the strong impact of the Si-cap growth time and temperature on the interface state density, which arises from the Si thickness dependence on these growth parameters. Furthermore, we successfully transfer a TmSiO/Tm 2 O 3 /HfO 2 gate stack process from Si to Ge devices with optimized Si-cap, yielding interface state density of 3·10 11 eV -1 cm -2 and a significant improvement in oxide trap density compared to GeO x passivation.

Introduction Germanium based transistors have attracted considerable research interest in recent years as one of the contenders for future CMOS technology nodes due to its high intrinsic electron and hole mobilities. Ge surface passivation with a thin silicon layer (Si-cap) has been shown to be efficient in terms of interface state density (Dit) and mobility, as well as advantageous over GeOx passivation regarding bias temperature instability reliability (1), (2). However, the performance of Si-passivated Ge devices is highly dependent on Si-cap growth conditions. For example, The Si-cap thickness is one of the key parameters in achieving low Dit. An optimal Si thickness in the range of 6-8 monolayers (ML) has been found for different gate fabrication schemes (3)- (6). In thick Si-caps, the interface state density degradation is related to plastic relaxation of the Si layer at around 12 ML thickness (7). On the other hand, when the Si-cap is thin, Ge segregation in the Si layer causes Dit generation (3), (4). It has been shown that hydrogen plays an important role in Ge segregation in the Si-caps (4), (8). In the presence of hydrogen, it is more energetically favourable for Si to be at the surface due to lower surface energy of H-covered Si than H-covered Ge. However, a H-free Ge surface has lower energy than H-free Si, giving rise to Ge surface segregation in H-free conditions. As a result, a low temperature hydrogen desorption limited Si-cap deposition process employing higher order Si precursors (Si2H6, Si3H8 or Si4H10) is needed. While Si-cap growth using Si3H8 (3), (4), (6), (7) and Si4H10 (6) have been explored, the studies of Si growth using the more cost-effective disilane (Si2H6) are mostly limited to ultra-high vacuum chemical vapour deposition (UHV CVD) (9)- (11). In addition, as the process window in terms of Si layer thickness is small and previous studies were performed at fixed temperatures, it is necessary to address the robustness  Science and Technology   1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 A c c e p t e d M a n u s c r i p t F o r R e v i e w O n l y of the process conditions needed to achieve such precise Si-cap thickness. Furthermore, the Sicap contributes to the capacitance equivalent thickness of the gate stack. Employing a high-k interfacial layer instead of a chemical SiO2 thus could be beneficial. Thulium silicate (TmSiO) as a replacement of SiO2 interfacial layer has been demonstrated in silicon gates with Dit ~10 11 eV -1 cm -2 (12), and we have also shown GeOx/Tm2O3 gate stacks with Dit < 5·10 11 eV -1 cm -2 (13). Hence, integrating TmSiO in Si-passivated Ge gates is a viable option.
In this paper, we evaluate the process window for Ge devices with Si-cap passivation using reduced pressure CVD from Si2H6 in the low temperature hydrogen desorption regime. We show that deposition time and growth temperature have a strong influence on the interface state density. Moreover, high-k TmSiO interfacial layer is integrated in the Si-cap process and Dit comparable to GeO2 passivation is demonstrated while simultaneously achieving low oxide trap density.

Experimental
All epitaxial layers in this work were grown in an ASM Epsilon 2000 CVD tool equipped with a cold wall lamp heated reactor. The temperature in the reactor is measured on the susceptor by thermocouples. The growth pressure was always kept at 20 Torr and the H2 carrier gas flow was kept constant at 20 slm. Ge strain relaxed buffers (SRBs) were grown on (100) Si wafers in a two-step process using a germane precursor (10 % GeH4 in H2) including a postepi thermal treatment at 890 °C (14) in order to create virtual substrates for Si growth. SRBs had a background doping concentration of ~10 15 cm -3 , RMS surface roughness < 1 nm and a threading dislocation density ~10 7 cm -2 . After n-type doping by using a phosphine precursor (5% PH3 in H2) a dopant concentration of ~1·10 16 cm -3 was achieved. The virtual substrates received an H2 bake at 850 ˚C for 10 min to desorb any residual Ge oxides before Si growth. The temperature was then slowly ramped down to the growth temperature in H2 ambient. Epitaxial Si layers were grown on Ge virtual substrates using a Si2H6 flow of 50 sccm at temperatures between 400 and 600 ˚C. After the Si growth, the temperature was ramped down from the growth temperature to <250 ˚C in H2 ambient before moving the wafers into the N2 purged unload station. The hydrogen coverage of the silicon surface reduces the initial oxidation of Si after unloading. The thicknesses of the Si-cap layers were measured immediately after the growth using spectroscopic ellipsometry. To interpret the ellipsometry measurements we assumed that the optical properties of the Si-cap layers were not affected by any plastic relaxation or surface roughness.
Si-passivated Ge MOS capacitors (MOSCAPs) were fabricated on Ge virtual substrates. Thin Si-caps were deposited at a nominal temperature of 400 °C as described above. The growth temperature was varied by ±3 °C in order to investigate the influence of Si growth temperature variation on the interface state density. In order to minimize Si-cap thickness consumption due to oxidation in air, 400 nm SiO2 was deposited by plasma-enhanced CVD at 400 °C immediately after unloading the wafers from the epitaxy reactor. Active areas were defined by lithography and reactive ion etching was employed to remove 350 nm of the SiO2 layer. After removing the remaining SiO2 from the active areas with 1 % HF solution, gate stack layers were deposited by atomic layer deposition (ALD) in a Beneq TFS 200 reactor equipped with a load lock. First, Tm2O3 was deposited at 225 °C using TmCp3 and H2O precursors (15) with a target thickness of 7.4 nm. Thulium silicate (TmSiO) interfacial layer A c c e p t e d M a n u s c r i p t F o r R e v i e w O n l y was then formed by rapid thermal anneal (RTA) at 550 °C for 60 s in N2. High-k ALD HfO2 was deposited using HfD04 and H2O precursors with a target thickness of 5.6 nm at 350 °C followed by a post deposition anneal (PDA) in O3 for 10 min. After 12 nm ALD TiN gate metal deposition at 425 °C (TiCl4 and NH3 precursors), a thick 500 nm Al was deposited by sputtering for electrical probing purposes followed by gate patterning. The device fabrication finished with a forming gas anneal (FGA) of 10% H2 in N2 at 400 °C for 30 min. The resulting gate stack is schematically depicted in Figure 1 (a) while Figure 1 (b) shows a cross-section TEM image of the gate stack with Si layer grown at the nominal temperature of 400 °C for 40 min. After Si reaction with Tm2O3 forming TmSiO of ~1 nm thickness, the remaining Si-cap has an approximate thickness of 0.5 nm. Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gate stacks were also fabricated by a similar process as in (13), with addition of ALD HfO2 and FGA.
Capacitance voltage (CV) measurements at 10-500 kHz frequencies were performed on the MOS capacitors with Cascade 12000 wafer prober and Keithley SCS 4200. Interface state density in the midgap was evaluated from CV characteristics at 10 kHz for 10 devices (each on a separate die) of each sample using a method described in (16).

Epitaxial growth of Si on Ge using disilane
In order to investigate Si growth with Si2H6 for Ge passivation, Si growth kinetics in 400-600 °C temperature range were studied. Figure 2 displays Si thickness as a function of the deposition time at growth temperatures between 400 °C and 500 °C. The thickness was measured on five points over a 100 mm wafer by spectroscopic ellipsometry, and the thickness uniformity (Range/Average) was <3 %. The Si thickness exhibits a linear time dependence, as indicated by simple linear regression. Linear growth dependence was also obtained for higher temperatures (not shown here). There is a clear incubation time before the Si growth starts and the incubation time was determined from the linear regressions intercept with the time axis, see Fig. 2. The incubation time decreases with increasing growth temperature, as shown in Fig. 3. It is possible that the observed incubation time is caused by the hydrogen coverage of the starting Ge surface which prevents Si nuclei formation initially. After a certain incubation period, Si nuclei form and Si growth continues with a constant deposition rate. Hydrogen coverage could also explain the temperature dependence of the incubation time. At higher temperatures, hydrogen surface coverage is lower causing the incubation time to drop, and above 500 °C incubation time becomes negligible. Only a very short incubation time was observed in literature (4) when N2 carrier gas was used for Si growth on Ge with silane (SiH4) at 500 °C where the growth rate was high initially and started to drop after 6-7 monolayers. The difference between these results could be attributed to the fact that when N2 carrier gas is used, the starting surface is not hydrogen terminated and Si nuclei can form faster. On the other hand, H2 carrier gas was used in this work. After the pre-epi anneal the temperature was ramped down to the growth temperature in H2 ambient, thus creating an H-terminated growth surface which can hinder the nuclei formation in the initial growth stage.
For Si-cap growth, higher hydrogen surface coverage is preferred because it reduces Ge segregation in the Si layer during the growth (4). As a result, temperatures below 475 °C are needed for Si-cap growth with Si2H6. Moreover, a careful estimation of the incubation time is required for precise Si-cap thickness control. Even lower growth temperature where incubation time is less temperature dependent (T ≤ 425 °C in Fig. 3) could thus be advantageous. Finally, low Si growth rate could also be beneficial for the precise control of the Si-cap thickness. Therefore, Si-cap growth at a nominal temperature of 400 °C has been adopted for Ge passivation in this work.

Process window for Ge passivation with Si-cap at 400 °C
In Si-passivated Ge devices, Si layer thickness plays a key role in determining the interface state density of the gate stack (3)-(5). If Si thickness deviates from the optimal value by even 1-2 monolayers, Dit increase by more than 1·10 12 eV -1 cm -2 can occur. Interface state density dependence on the Si-cap growth time at a nominal temperature of 400 °C is displayed in Fig. 5. The lowest interface state density of 3·10 11 eV -1 cm -2 is achieved at the optimal growth time of 40 min, and increases for both shorter and longer growth times. As shown above, epitaxial Si growth rate at temperatures below 475 °C exhibits an exponential temperature dependence with an activation energy EA = 2.0 eV. A one degree temperature deviation from the nominal temperature could then change the growth rate by 5 % while a three degree deviation by as much as 14 %. Therefore, small temperature deviations could potentially alter the Si layer thickness significantly enough to increase the interface state density of the gate stack. In this section, the process window for Ge passivation with Si-cap grown at 400 ˚C is investigated.
The influence of Si-cap growth temperature on Dit was investigated by introducing a small (up to ±3 ˚C) deviation from the nominal growth temperature of 400 ˚C while keeping the growth time constant at 40 min, as this growth time gave the lowest interface state density (Fig.  5). The interface state density as a function of the deviation from the nominal temperature and in turn as deposited Si-cap thickness is displayed in Fig. 6 where each point shows an average over 10 MOSCAPs and the error bars indicate the range. Si-cap thickness was calculated in the following way. First the growth rate was estimated from the temperature deviation given EA = 2.0 eV. Then the thickness was calculated assuming that the incubation time is not dependent on temperature in such a small temperature interval. Finally, the thickness was converted into  Science and Technology   1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 A c c e p t e d M a n u s c r i p t F o r R e v i e w O n l y monolayers assuming 1 ML = 1.3 Å for strained Si on Ge. Note that by performing this conversion, non-discrete ML thickness can be obtained. This thickness should be regarded as an average thickness over the surface steps of one (or more) ML height, which then corresponds to non-discrete thickness in ML. Also note that Fig. 6 displays the deposited Si-cap thickness, which after TmSiO formation is reduced by ~4 ML. As evident from Fig. 6, even one degree deviation from the nominal temperature increases Dit 1.5-2 times, from 3·10 11 eV -1 cm -2 to 4.5·10 11 eV -1 cm -2 and 6.5·10 11 eV -1 cm -2 for -1 ˚C and 1 ˚C deviation, respectively. The average thickness change due to 1 ˚C temperature deviation corresponds to 0.4 ML. It is larger than the Si thickness variation over a wafer, which corresponds to 0.25 ML for Si-cap grown at 400 °C for 40 min. If the growth temperature deviates from the nominal temperature more (±3 ˚C), the Si-cap thickness changes by 1.2-1.4 ML and Dit rises to above 10 12 eV -1 cm -2 . This result is consistent with the interface state density dependence on Si-cap thickness reported in literature for Si growth with SiH4 and Si3H8 (3)-(5). When Si-cap thickness deviates from its optimal value, the interface state density not only degrades but also becomes less uniform within a wafer. At the nominal growth temperature, the range is 8·10 10 eV -1 cm -2 while at ±3 ˚C deviation from the nominal temperature, the range is more than 5·10 11 eV -1 cm -2 . This could be explained by Si thickness variation over a wafer. When Si-cap thickness is close to an optimal thickness, small thickness variations over a wafer have little influence on the Dit. On the other hand, when Si thickness is far from optimal, the relative thickness variation will give a similar relative Dit variation which then results in higher Dit range.
To further investigate the influence of the process parameters on the interface state density in Si-passivated gate stacks, Si-cap deposition time was varied. The interface state density in Ge gates with Si-caps grown at three different temperatures (nominal 400 °C ± 1 °C) for 30-60 min is depicted in Fig. 7 as a function of the grown Si-cap thickness. Here the Si-cap thickness was calculated in a similar manner as described above. The lowest Dit is achieved at 8-9 ML initial Si-cap thickness indicated by a green rectangle. The interface state density increases as the Si-cap thickness decreases, reaching around 10 12 eV -1 cm -2 at 6 ML initial thickness. Note that due to Si consumption during TmSiO formation this thickness is estimated to be around 2 ML in the fabricated device. The interface state density degradation could be associated with previously reported Ge surface segregation in thin Si-caps (3), (4). Even though hydrogen surface coverage at 400 °C reduces Ge surface segregation (4), (8), some intermixing of Ge and Si can still occur in the thin Si-cap. Moreover, in very thin Si-caps the whole Si layer could be consumed during TmSiO formation, also increasing the interface state density. An increase in the interface state density is also observed in Ge gates with initial Si thickness higher than 9 ML, where Dit reaches more than 10 12 eV -1 cm -2 in gates with Si-caps thicker than 12 monolayers. The increase in the interface state density is consistent with the plastic relaxation that has been reported to occur above 12 ML thickness (7).
The process window, when the interface state density is below 5·10 11 eV -1 cm -2 , is defined by both growth temperature and time, and corresponds to between 8 and 9 ML initial Si-cap thickness. For a given growth time, a temperature deviation in the epi-reactor of even one degree (+1 °C in Fig. 7) can alter the Si layer thickness enough to be detrimental to the interface state density. Hence, temperature control when depositing Si-caps for Ge surface passivation is of a paramount importance for achieving low interface state density. Care should be taken to maintain a precise temperature in the epi-reactor, especially after routine temperature  1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 A c c e p t e d M a n u s c r i p t F o r R e v i e w O n l y calibrations and reactor cleans. Alternatively, extending the process window could ensure low Dit even if small temperature drifts occurred. Expanding the process window for thicker Sicaps is not an option due to the plastic relaxation of the Si layer. On the other hand, thinner Sicaps could be employed if Si consumption during the TmSiO process would be limited, e.g. by lowering the silicate formation temperature.

Ge MOS capacitors with optimized Si-cap and TmSiO interfacial layer
In the previous section we have identified that at the growth temperature of 400 ˚C the optimum Si-cap thickness is achieved at 40 min growth time. Ge MOS capacitors fabricated with this Si-cap process demonstrated the lowest interface state density. One of the challenges in Ge gate stacks is to simultaneously achieve high mobility and adequate reliability. While low interface state density is a good indication of high mobility, low oxide trap density can show a potential for superior reliability. For this reason, Ge MOS capacitors with optimal Sicap thickness were further electrically characterized to determine the oxide trap density Nox and compared to GeO2 passivated Ge MOS capacitors.
Well behaved CV characteristics of a typical MOS capacitor with Ge/Si/TmSiO/Tm2O3/HfO2/TiN gate are displayed in Fig. 8 (a). Almost no frequency dispersion is observed. Interface state density and equivalent oxide thickness were extracted from CV characteristics of 10 MOSCAPs over a 100 mm wafer. Dit in the midgap was found to be ~3·10 11 eV -1 cm -2 and EOT of 3.7-3.8 nm as displayed in Fig. 8 (b). Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gates exhibit a similar Dit of 2·10 11 cm -2 eV -1 . The interface state density of Si-passivated Ge gates is also consistent with TmSiO/Tm2O3 gate stacks previously shown on Si, which yielded Dit ~10 11 eV -1 cm -2 (12), demonstrating that no significant Dit degradation occurs when transferring the gate stack process to Si-passivated Ge. The interface state density in the midgap represents the overall Dit tendency while future work could explore the interface state density near the band edges and determine the suitability of the gate stack for pFET or nFET aplications.
Oxide trap density Nox in both Si-cap and the reference GeOx MOS capacitors was extracted from the hysteresis ΔV of a dual CV sweep. Dual CV sweep of a typical Si-passivated MOS capacitor is shown in Fig. 9 (a) while Fig. 9 (b) displays Nox as a function of the oxide electric field Eox which is defined as: Here VG,max is the highest voltage to which the dual sweep was performed, VFB is the flatband voltage and CET is capacitance equivalent thickness. The Si-passivated gates exhibit a hysteresis of only ~3 mV at Eox of 4 MV/cm corresponding to Nox of 1.5·10 10 cm -2 . It is more than 20 times lower than the oxide trap density of the reference GeOx devices, showing the superiority of Si-passivated gates. Low oxide trap density in Ge/Si/TmSiO/Tm2O3/HfO2/TiN gate stacks indicates a potential for improved reliability. This makes Si-passivated Ge gates with high-k TmSiO interfacial layer a viable candidate for future CMOS technology due to their potential for both high mobility and superior reliability.