Electron Charge Transport in Non-Peripherally Substituted Copper Phthalocyanine

Bottom-gate, bottom-contact organic thin ﬁ lm transistors (OTFTs) were fabricated using solvent soluble copper- 1,4,8,11,15,18,22,25-octakis(hexyl)phthalocyanine as the active semiconductor layer. The compound was deposited as 70 nm thick spin-coated ﬁ lms onto gold source-drain electrodes supported on octadecyltrichlorosilane treated 250 nm thick SiO 2 gate insulator. The analysis of experimental results showed the n-type ﬁ eld effect behaviour. Devices annealed at 100 o C under vacuum were found to exhibit the ﬁ eld-effect mobility of 0.0989 cm 2 V − 1 s − 1 , with an on/off current modulation ratio of ∼ 10 6 , a reduced threshold voltage of 0.7 V and a sub-threshold swing of 2.12 V decade − 1 . The variations in surface morphology of the devices are found re ﬂ ected considerably in the electrical measurements. The device contact resistance was found to be decreased as the gate bias increased and also with the annealing.

In recent years, organic field-effect transistors (OFETs) have been extensively used in designing complementary integrated circuits for flexible smart cards, low-cost radio frequency identification (RFID) tags, and organic active matrix displays and sensors. 1 Fullerene derivatives are found to be good materials for the formation of n-type conducting channels. 2 For example, a value of --0.34 cm V s 2 1 1 for electron mobility is reported for the Faux-hawk fullerenes (C 60 FHF) channel. 3 Alternatively perylene diimides (PDIs) and naphthalene diimides (NDIs) are the most promising electron deficient building blocks for obtaining high performance electron transport materials with high mobilities of --6.2 cm V s 2 1 1 due to their relatively high electron affinities, and excellent chemical and thermal stability. 4 Solution processable organic and polymeric semiconducting materials are attractive to realize low-cost, high-volume, large-area electronic circuits on flexible substrates. Several solution based processes, such as spin-coating, drop-casting, and inkjet printing can be used to form semiconducting thin films. Bottom-gate, top-contact OTFTs with NDI active layers were fabricated based on OTSmodified SiO 2 substrates and extremely high electron mobility up to --7.5 cm V s 2 1 1 was achieved. 5 Representative examples of PDI derivatives with thin film mobilities over  Bottom-gate, top-contact OTFTs were fabricated with a NDI on OTS-modified SiO 2 substrates, and extremely high electron mobility up to ---7.5 cm V s 2 1 1 was achieved when the devices were tested after 30 min equilibration in an argon atmosphere at low humidity. 7 Small molecules based on azulene derivatives, dicyanomethyleneterminated quinoidal oligothiophenes, and isoindigo derivatives (3E,7E)−3,7-bis(2-oxoindolin-3-ylidene)benzo[1,2-b:4,5-b′]difuran-2,6(3 H,7 H)-dione have been investigated for their uses as ntype active layers in OFETs, producing mobility in the order of --0.1 cm V s . 2 1 18 When[6,6]-phenyl C61 butyric acid methyl ester is doped with (4-(1,3dimethyl-2,3-dihydro-1H-benzoimidazol-2-yl) phenyl)dimethylamine, the electron mobility is found to increase from´--- 1 has recently been reported for electron mobility for phenylalkyl-substituted-benzo[de]isoquinolino [1,8-gh] quinolinetetracarboxylic diimide. 9 Phthalocyanines, highly conjugated 18 π-electron planar aromatic systems with a central cavity of sufficient size capable of coordinating different metal ions, are thermally and chemically stable and show excellent semiconducting properties for their applications including the fabrication of OTFTs. 10  1 is obtained for electron mobility of thermally deposited bis(pentafluorophenoxy) silicon phthalocyanine(F-10-SiPc) at  140 C. 12 Electron mobilities of OTFTs with a n-type polycrystalline channel of tin phthalocyanines (SnPcs) with tributylsilane and trihexylsilane axial functional groups is found to be higher than their silicon counterparts due to increased molecular interactions. 13 The introduction of substituents onto the phthalocyanine nucleus can confer new and useful properties upon the ring system. 14 The present paper reports an investigation of n-type field-effect transistor characteristics of non-peripherally octakis(hexyl) substituted copper phthalocyanine (6CuPc) derivative in the bottom gate transistor configurations as shown in Fig. 1. As reported before, the solubility of these molecule in common organic solvents enabled it to be deposited readily as well-ordered films by the spin coating method, a methodology ideal for simple device fabrication at room temperature. 15 Hole transport in spin coated 6CuPc has been investigated in OTFTs of similar configurations, giving p-type characteristics in the accumulation mode. These molecules are liquid crystalline and the transistor parameters are reported to be dependent upon the annealing temperature. Devices heat treated at 100°C under vacuum (⩾10 −7 mbar) were found to exhibit the highest field-effect mobility of 0.7 cm 2 V −1 s −1 , with an on-off current modulation ratio of 10 7 , threshold voltage of 2.0 V and a sub-threshold swing of 1.11 V per decade. 16

Experimental
The drift mobility m de was determined from the time of flight (TOF) measurement for the electron transport in a m 9.1 m thick film z E-mail: n.chaure@physics.unipune.ac.in of 6CuPc sandwiched between two transparent indium tin oxide (ITO) coated glass substrates. The cell was formed by slow cooling of the organic layer at a rate of 2°C min −1 to room temperature from the isotropic melt and a film of anti-parallel polyimide was used as the alignment layer. The photocurrents were produced using a 532 nm pulsed output of a double-frequency Nd:YAG laser to excite the sample. The bias between the ITO electrodes was provided by a DC power supply while the transient photocurrent was recorded by a voltage drop across the input resistor of a gain 11 amplifier circuit whose output was connected to an Agilent Infinium digitizing oscilloscope. Signal averaging was carried out on all signals in order to improve data quality. 17 As shown in Fig. 1b, measurements of the n-type transistor characteristics have been performed under identical conditions on bottom gated organic field effect transistors using both as-prepared and annealed 70 nm (± 2 nm) thick spin-coated active layer 6CuPc films on the pre-patterned source and drain electrodes and 250 nm thick octaoctadecyltrichlorosilane (OTS) passivated SiO 2 gate dielectric layer on the highly doped silicon (110) gate electrode substrates. Two stage spin coater, Chemat Technology Inc., Model KW-4A was employed to prepare the uniform 6CuPc thin films initially at 1000 rpm for 30 s and subsequently 3000 rpm for 60 s. The devices were heated to  100 C in a tubular furnace under vacuum of~´-2 10 Torr 7 and then gradually cooled down to room temperature at the rate of  -1 C min . 1 The electrical measurements were performed at room temperature in air under ambient conditions using a Keithley 4200 semiconductor parameter analyzer with three source measure units (SMUs), which allows to measure the source, drain and gate currents simultaneously. All measurements were performed at a typical scan rate 50 m V s −1 . A custom-made probe station was used to obtain the source, drain and gate contacts. Prior to electrical measurement the devices were blew with N 2 gas and all equipments commonly grounded to probe station. 18 The surface morphology of the sample was investigated by the Digital Nanoscope III, Atomic Force Microscope (AFM) in non-conducting mode at ambient conditions using V-shaped silicon nitride cantilevers with force constant 2 N/m and resonance frequency 315 kHz.

Results and Discussion
The AFM micrographs o as-prepared and annealed 6CuPc spin coated film on Silicon substrate is shown in Figs. 2a and 2b, respectively. Both films illustrate significantly void free, densely packed compact good film adhesion to the 15 mm × 15 mm area of silicon substrate. Long grain like flat lying crystals of size ∼0.1 μm can be seen in as-prepared sample. Randomly oriented short nanorods ∼0.3 to 0.4 μm were observed upon annealing the devices at 100  C in vacuum. The rod like morphology reduces apparent grain boundaries and may behave like a compound in the bulk material. Further, the rod like morphology is assumed to be supportive for charge transportation within the active semiconductor, which of course helps to improve the mobility of device. Root mean square values of 9 nm and 17 nm were measured for surface roughness of as-prepared and annealed 6CuPc films, respectively. The number of grain boundaries influences the electrical properties of devices. Rosenwaks and co-worker showed for the accumulation of charge carriers at the grain boundaries for pentacene films using Kelvin probe measurements leads to lower mobility of FETs. 19 Klauk and co-worker have reported that the grain boundaries are major source of degradation of charge carries mobility in C 3 F 7 CH 2 −PTCDI-(CN) 2 based p-channel devices. 20 Larger grain size obtained for pentacene on poly-4-vinylphenol than polymethyl methacrylate gate dielectric measured higher mobility. 21 The transit times t 0 of the photo-generated carriers traversing the 6CuPc layer at an applied bias, were determined by the inflection point on a double logarithmic plot. The resulting mobilities μ were then calculated using the relation, where d is the cell thickness and V is the applied bias. Electron transport was measured in the sample at 0.40 μs and 0.26 μs for −6 V and −10V, respectively (Fig. 3a). Further analysis of the sample at higher fields for both electron transport, could not be carried out at room temperature as the inflexion point became engulfed in the initial peak of the photocurrent. The mobilities were calculated using Eq. 1 and plotted against the square root of the electric field (Fig. 3b). Electron mobility is found to be 0.4 cm 2 V −1 s −1 . This value is three orders of magnitude higher than one obtained for similar configured 2 μm thick 6ZnPc drop-cast films. 22 This relatively high mobility is attributed to the larger, well defined 6CuPc crystallites formed during slow cooling of the sample. For both bias voltages, the photo-current is found to have progressively decreased over time. However, the decrease is steeper for V a = 10 V than V a = 23 V, indicating the dominance of dispersive transport. The time of flight method gives a "long-range" mobility measured over relatively large distances (usually tens of microns) and on a milli-second or micro-second timescale. This dispersive behaviour is consistent for the multi-domain film structure, consisting of a large number of boundaries between domains with typically 300 nm to 400 nm cross-section as recorded under a polarizing microscope. A typical set of output characteristics of drain-to-source current I DS vs drain-to-source voltage V DS for different values of the gate voltage V G of as-prepared and annealed devices are shown in Figs. 4a and 4b, respectively. The variations in surface morphology of the devices are found reflected considerably in the electrical measurements. Both devices demonstrated a typical n-type behaviour operating in accumulation mode with the increase in the drain current I DS with V G . 23 A significant improvement in the performance of thermally annealed device at 100°C is observed due to the coalescence of small grains having low surface energy leading to improve crystallinity and less grain boundaries. A clear transition from linear to saturation region was observed for annealed device due to pinch-off of the accumulation of charges. It was further observed that the I DS in annealed device saturated at lower I DS as compared to the corresponding value of as-prepared device. The annealing temperature was chosen based on the differential scanning calorimetry studies discussed in our earlier publication. 16 The transfer characteristics, drain-to-source current, I DS and square root of drain current, (I DS ) 1/2 as a function of gate voltages, (V G ) with constant drain voltages in linear regime, V D = 5 V and saturated regime, V D = 40 V for as-prepared and annealed devices are shown in Figs. 5a and 5b, respectively. The performance parameters of 6CuPc FET were extracted from the saturated and linear regimes by using the Eqs. 2 and 3.
where L, W and C i are the channel length (10 μm), channel width (2 mm) and capacitance/unit area taken to be 1 × 10 −4 F m −2 for the OTS treated SiO 2 gate dielectrics. 24 m sat and m lin are saturated and linear field effect mobility, V T is the threshold voltage of the device in both linear and saturated regime were determined from the graph of I DS vs V G by extrapolating the straight line to I DS = 0. The values of linear and saturated field effect mobility, μ lin and μ sat were extracted from the trans-conductance plot shown in Figs. 5a and 5b.
The values of mobilities of as-prepared and annealed devices are given in Table I. The value of m lin was comparatively lower than that of m . sat However, the value of m lin is found to be increased by one order of magnitude from 3.69 × 10 −3 cm 2 V −1 s −1 for OFFT with as-prepared channel to´-   prepared device. These experimental results show the decrease of the resistance of the conducting channel with large grain boundaries leading to a performance improvement of the OTFTs. 25 The transistor characteristics of an n-type OTFT using physical vapour deposited N hexdecafluoro copper phthalocyanine (16-CuPc) films as active layer have recently reported. Values of saturation mobility m sat threshold voltage V T and on-off ratio are found to bé 1 -16 V and3 10 , 3 respectively. In this context, 6CuPc OTFTs have produced the characteristics of improved performance. 26 Kraus et al., and de Boer et al., showed the ambiploar behaviour of CuPc OFETs prepared by thermal evaporation technique with electron mobility to 5.8 × 10 −3 and 10 −5 -10 −3 cm 2 V −1 s −1 , 27,28 which is considerably less than the electron mobility, 9.89 × 10 −2 cm 2 V −1 s −1 measured for our devices.
The transfer characteristics exhibited good sub-threshold slopes. The sub-threshold voltage, S gives the information about the gate voltage required to increase the drain-to-source current by a factor of 10. The values of sub-threshold voltages, 3.65 V decade −1 and 2.12 V decade −1 were estimated using the following equation for as-prepared and annealed 6CuPc transistors within saturated regimes, respectively.
The performance parameters of the transistor also depend on the grain size, grain boundaries and the interface between the gate dielectric (SiO 2 ) layer and active semiconductor (6CuPc) thin film. The density of trapped charges (trap charge density (N t ) can be determined by using the following relation related to sub-threshold voltages: where k, T, q and S are the Boltzmann constant, the operating temperature, the electronic charge and the sub-threshold voltage swing, respectively. The values of density of trap, N t were calculated to be 1.99 × 10 12 cm −2 eV −1 and 2.23 × 10 11 cm −2 eV −1 for asprepared and annealed devices in the saturated regime. The decrease in value of N t upon annealing is believed to be due to reduction in grain boundaries. 29   The relation between I DS and the charges trapped at the grain boundaries of the material is described by Levinson model. 30 The Levinson plots of ln(I D /V G ) vs 1/V G at V D = 40 V for as-prepared and annealed 6CuPc devices are shown in Fig. 6. The linear behaviour of the graph demonstrates the dependence of I DS on the density of traps at the grain boundaries, N g .
The values of N g and trap-free mobility, μ 0 can be extracted from the slope and intercept to x-axis at 1/V G = 0, respectively. The values of free space permittivity, ε o = 8.85 × 10 −12 F m −1 , electronic charge, q = 1.6 × 10 −19 C, Boltzmann constant, k = 8.62 × 10 −5 eV K −1 , temperature, T = 300 K and dielectric constant, ε pc = 3 of 6CuPc were used to determine values of N g . The values of 6.56 × 10 12 cm −3 and 8.72 × 10 11 cm −3 were estimated for N g , from the slopes of best linear fits of Levinson plots. As shown in Fig. 7, the value of N g obtained for annealed device is smaller than that of as-deposited film by nearly a one order of magnitude. This observation is associated with the less dense presence of grain boundaries upon thermal annealing. The values of trap-free mobilities, 0.882 × 10 −2 and 2.26 × 10 −2 cm 2 V −1 s −1 at V D = 40 V were calculated for as-prepared and annealed 6CuPc devices. The grain boundary barrier = e e E B q N t 8 CV 3 g 2 0 Pc i G decreases while the grain boundary mobility μ GB increases with V G . E B is found to undergo sharp decreases at low voltages and then the reduction tends to be steady. The density N g is believed to contribute to the parasitic resistance of the device.
The contact resistance R C can be expressed at each gate voltage in the following form 31 : The linear regions of the output curve can be used to determine the values of total resistance (R total ) for different gate voltages. The linear mobilities, 0.00369 and 0.0487 cm 2 V −1 s −1 computed with V D = 5 V for as-prepared and annealed transistors, respectively along with corresponding V G and V T were used. The contact resistances as a function of gate biases shown in Fig. 8 revealed that the contact resistance decreases with increasing the gate bias. The decrease in contact resistance at higher gate biases could be due to the higher charge density in the conducting channel and in the vicinity of contacts. These results are consistent with the observations reported by Zhang et al. 32 Upon annealing the contact resistances obtained for each gate bias decreases substantially due to the coalescence of small grains, results the improvement in degree of crystallinity and less grain boundaries.

Concluding Remarks
6CuPc molecules are liquid crystalline and remain well aligned in the spin coated film with their columnar axis parallel to the substrate. This technique of thin film deposition may easily be adopted for the deposition over a large area for flexible electronics. The disordered film structure is evident from AFM images, following the annealing temperature dependent growth of crystallites in different shapes, sizes and orientations. The variations in surface morphology of the devices are found reflected considerably in the electrical measurements. The drain-source current is believed to be one dimensional electron transport via the overlap of π-π molecular orbitals through the accumulation layer. This investigation is interesting for the development of organic complementary metal oxide semiconductor (CMOS) circuits and organic light-emitting transistors.