Abstract
The excellent performance of n-channel thin film transistors (TFTs) based on amorphous oxide semiconductors has allowed integrated circuits based on NMOS logic to be successfully realized. However, future development will require CMOS logic to avoid excessive power dissipation and therefore p-channel TFTs are needed. Thin film p-type oxide semiconductors are rarely amorphous, and their microstructure has a significant impact upon both hole mobility and off-state current. In silicon MOSFETs, it is possible to scale device geometry to compensate for the lower hole mobility relative to electron mobility, but in TFTs this results in an excessive off-state current in the p-channel TFT as the off-state current also scales with geometry, which is not true to the same degree in silicon MOSFETs. Using new scaling rules that account for the off-state current, it is possible to optimize p-channel TFTs to operate alongside n-channel TFTs to achieve low power CMOS logic.