3D Suspended Nanowires Integration for CMOS and Beyond

Thomas Ernst; Kiichi Tachi; Alexandre Hubert; Emeline Saracco; Cécilia Dupré; Stéphane Bécu; Nathalie Vulliet; Emilie Bernard; Peter Cherns; Virginie Maffini-Alvaro; Jean-François Damlencourt; Christian Vizioz; Jean-Philippe Colonna; Caroline Bonafos; Jean-Michel Hartmann

doi:10.1149/1.3203985

ECS Transactions

3D Suspended Nanowires Integration for CMOS and Beyond

Thomas Ernst¹, Kiichi Tachi¹, Alexandre Hubert¹, Emeline Saracco¹, Cécilia Dupré¹, Stéphane Bécu¹, Nathalie Vulliet², Emilie Bernard¹, Peter Cherns¹, Virginie Maffini-Alvaro¹, Jean-François Damlencourt³, Christian Vizioz¹, Jean-Philippe Colonna¹, Caroline Bonafos¹ and Jean-Michel Hartmann¹

© 2009 ECS - The Electrochemical Society
ECS Transactions, Volume 25, Number 7 Citation Thomas Ernst et al 2009 ECS Trans. 25 471 DOI 10.1149/1.3203985

Download Article PDF

Article metrics

12 Total downloads

Permissions

Get permission to re-use this article

Author affiliations

¹ CEA-LETI

² STMicroelectronics

³ CEA LETI MINATEC

Journal RSS

Sign up for new issue notifications

Abstract

Novel 3D stacked Gate-All-Around (GAA) nanowires CMOS architectures were developed recently for their very low leakage potentialities and high current drivability for sub-22nm nodes. In this paper, we will discuss some challenges and innovations associated to such devices integration as well as their potential applications.

Export citation and abstract BibTeX RIS

Previous article in issue

Next article in issue

3D Suspended Nanowires Integration for CMOS and Beyond

Article metrics

Permissions

Share this article

Author affiliations

Abstract