Dry Etch Challenges in Gate All Around Devices for sub 32 nm Applications

Sebastien Barnola; Christian Vizioz; Nathalie Vulliet; Cécilia Dupré; Thomas Ernst; Pauline Gautier; Christian Arvet; Bernard Guillaumot; Emilie Bernard; S. Pauliac-Vaujeour; Corine Comboroure; Jean-Michel Hartmann; Stephan Borel; Thierry Chevolleau; V Maffini-Alvaro; S Becu

doi:10.1149/1.2986854

ECS Transactions

Dry Etch Challenges in Gate All Around Devices for sub 32 nm Applications

Sebastien Barnola¹, Christian Vizioz¹, Nathalie Vulliet², Cécilia Dupré¹, Thomas Ernst¹, Pauline Gautier¹, Christian Arvet², Bernard Guillaumot², Emilie Bernard², S. Pauliac-Vaujeour², Corine Comboroure³, Jean-Michel Hartmann⁴, Stephan Borel¹, Thierry Chevolleau⁵, V Maffini-Alvaro⁴ and S Becu¹

© 2008 ECS - The Electrochemical Society
ECS Transactions, Volume 16, Number 10 Citation Sebastien Barnola et al 2008 ECS Trans. 16 923 DOI 10.1149/1.2986854

Download Article PDF

Article metrics

90 Total downloads

Permissions

Get permission to re-use this article

Author affiliations

¹ CEA-LETI-Minatec

² STM/CEA-LETI-Minatec

³ CEA-Leti MINATEC

⁴ CEA-LETI MINATEC

⁵ CNRS-LTM

Journal RSS

Sign up for new issue notifications

Abstract

We present a novel approach to pattern aggressive aspect ratio Si/Si1-xGex superlattices on Silicon On Insulator (SOI) wafers. This approach is based on the anisotropic etching of Si/SiGe superlattices with final dimensions down to 30nm, and the isotropic etching of the SiGe selectively to silicon. This isotropic etching was developed in a remote plasma chamber, and in-situ in an Inductive Coupled Plasma (ICP) reactor.

Export citation and abstract BibTeX RIS

Previous article in issue

Next article in issue

Dry Etch Challenges in Gate All Around Devices for sub 32 nm Applications

Article metrics

Permissions

Share this article

Author affiliations

Abstract