Impact of Forming Gas Annealing and Firing on the Al₂O₃/p-Si Interface State Spectrum

One of the first so-called high-k dielectrics that received considerable research interest from the Complementary Metal-Oxide-Semiconductor (CMOS) scaling community was Al₂O₃.^{1, 2} When screening high-k materials for the fabrication of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), Al₂O₃ appears to be a good candidate because of its excellent dielectric properties – a high band gap and a reasonable high k value – its strong adhesion to dissimilar materials and its thermal and chemical stability. This explains the strong research interest in the interface and trapping properties of the Al₂O₃/Si system at some point in time.^3–5 Meanwhile, it has become clear that for device scaling alternative high-k materials offer better perspectives, but at the same time, SiO₂/Al₂O₃ bilayer stacks can also be employed for the development of non volatile memories.^{6, 7} Quite recently, it has been demonstrated that the negative fixed oxide charge in Al₂O₃ is favorable for reaching a good field-induced surface passivation of p-type silicon for solar cell applications.^8–10 This has triggered quite some investigations on the electrical properties of the Al₂O₃/Si system^11–17 and it has been pointed out that both chemical and field-effect passivation play a role in the improvement of the surface recombination properties.^{8–10, 18, 19} A related point of interest is whether the density of interface states (D_it) can be reduced by hydrogen passivation, using for example a post-Al-metallization Forming Gas Anneal (FGA).^20–22 At the same time, one should address the question of the stability of the Al₂O₃ properties under a high temperature firing process, which is typically applied between 700 and 850°C.²⁰

The present work investigates the interface properties of Al/Al₂O₃/p-Si Metal-Oxide-Semiconductor (MOS) capacitors after various processing steps, namely, as-deposited, after a 30 min FGA (10% H₂ in N₂) at 350°C and after a firing step, consisting of a Rapid Thermal Processing (RTP) with a peak temperature above 800°C for 1–2 s.²³ The FGA and firing steps have been applied after Al gate deposition. Initial results on the surface recombination properties have been recently reported.²⁴ Deep-Level Transient Spectroscopy (DLTS) is used to generate a D_it distribution versus activation energy with respect to the valence band edge E_V. Earlier studies on Atomic Layer Deposited (ALD) 5.8-nm thick Al₂O₃ layers revealed deep-level peaks at 0.19, 0.24, 0.29 and 0.37 eV, respectively.²⁵ At the same time, it was observed that a FGA at 450°C reduced the D_it significantly from 10₁₂ cm₋₂eV₋₁ to 4 × 10₁₁ cm₋₂eV₋₁ at E_V + 0.35 eV. It is shown here that both FGA and firing of 5 nm Al₂O₃ layers result in a clear reduction of the D_it, whereby also the activation energy, corresponding with the DLTS peak maximum reduces. A similar behavior is observed for 5 nm thermal SiO₂ reference samples, indicating that the observed interface states are related with the thin interfacial SiO₂ layer which is formed upon Al₂O₃ deposition.

Before deposition, the 200 mm diameter p-type Czochralski Si substrates were cleaned in a hot H₂O₂:H₂SO₄ 1:4 solution, followed by an HF-dip and a water rinse. Forty cycles of ALD Al₂O₃ was performed in a Savannah tool at 200°C, with H₂O as the oxygen precursor and trimethyl-aluminum (TMA) as the Al precursor, resulting in a thickness of 5 nm. The pulsing sequence was H₂O, TMA, H₂O. This was followed by the sputtering of 500 nm thick Al gate electrodes with different diameters. The 5 nm SiO₂ reference capacitors were fabricated using in-situ steam generated oxidation at 850°C.

Before DLTS, 1 MHz Capacitance-Voltage (C-V) and Current-Voltage (I-V) measurements have been performed at room temperature in order to define a proper bias-pulse range for the DLTS measurements. It turns out that the typically 500 μm diameter Al capacitors generally suffer from a rather high forward gate leakage current from the 1 μA to the several 100 μA range at −2 V, which affects the 1 MHz C-V characteristics in the accumulation region, as shown in Fig. 1. The tendency for leaky devices increased for the FGA or fired samples, suggesting a correlation with the damaging or degradation of the oxide by creating trapping centers. For reasons of sample-mounting in the DLTS holder, only large-diameter (≥400 μm) dots could be handled. Whenever possible, capacitors with low gate current have been characterized by DLTS. Alternatively, a pulse bias V_P was chosen sufficiently into accumulation to fill the interface traps but avoiding a high gate current (e.g. >−1 V in Fig. 1), which may result in electron injection and recombination and gives rise to negative, minority-carrier deep-level peaks.

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DLTS has been performed using a Fourier-Transform-based digital system. Spectra have been obtained either from a frequency scan at room temperature or a temperature scan from 75 to 320 K, typically, whereby the capacitors are repetitively pulsed from a depletion bias (V_R) into accumulation (V_P), during a pulse time t_p. Further experimental details have been reported before.^{26, 27}

According to the isothermal DLT-spectra of Fig. 2, a pronounced deep-level peak is observed in the as-deposited samples at room temperature. It is also clear that the associated traps occur at the Al₂O₃/p-Si interface since the spectrum recorded in depletion from 4 to 2 V, which only probes traps in the Si substrate, is essentially flat. After FGA or firing, the magnitude of the peak has drastically reduced, suggesting partial passivation of the underlying interface states by atomic hydrogen. At the same time, the peak maximum shifts to a lower sampling period t_w, indicating a lowering of the activation energy towards the valence band. Note that in Fig. 2 the DLTS amplitude has been divided by the steady-state capacitance in order to have a better quantitative comparison of the spectra for the different samples.

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Since the spectra of Fig. 2 are associated with interface states, a D_it spectrum can be calculated, following the procedures outlined elsewhere.^{26, 27} The result is displayed in Fig. 3, confirming the conclusion derived from Fig. 2, namely, that FGA and firing lowers the D_it at the Al₂O₃/p-Si interface and at the same time moves the distribution towards lower activation energies. In the calculation of the activation energy, a constant hole capture cross section of 10₋₁₅ cm₂ was taken, which corresponds with the energy-averaged value, that has been derived from the intercept of the Arrhenius plots obtained from small-pulse-height measurements as a function of temperature. The peak D_it values for the as-deposited Al₂O₃ sample are rather high, but are on the same order of magnitude as was reported recently for plasma ALD and O₃-ALD, where C-V measurements revealed densities in the range ∼10₁₃ eV₋₁cm₋₂.²⁸ However, much lower values on the order of 3 × 10₁₁ eV₋₁ cm₋₂ have been found for H₂O-ALD layers on p-Si.²⁸ In addition, a D_it below 10₁₁ eV₋₁cm₋₂ was reported for as-deposited H₂O-ALD Al₂O₃ layers from conductance measurements using a mercury probe.²⁹ This suggests that the Al-gate deposition may also be partly responsible for the "as-grown" D_it.³⁰ Previous reports demonstrated a significant lowering of the D_it by FGA at the Al₂O₃/p-Si interface.^{22, 28} At the same time, it is shown that a low D_it is also obtained after a firing step only, in perfect agreement with the observations of Benick et al. and confirming the stability of the surface passivation after solar cell processing.²⁰

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Comparing the D_it distribution of Fig. 3 for Al₂O₃ capacitors with the 5 nm SiO₂ reference samples in Fig. 4, one can conclude that rather similar results are obtained in both cases: a reduction of the D_it upon FGA and a shift towards lower activation energies. Note that according to the data of Figs. 3 and 4, FGA seems to be more effective in the case of Al₂O₃, which could be related to the presence of atomic H in the high-k layer coming from the H₂O precursor. Note that the peak D_it value for as-grown SiO₂ is on the high side, compared with data obtained on 25 nm SiO₂ layers on p-type Si.³¹ Especially after FGA, the remaining D_it is still rather high indicating that the hydrogen passivation is not so effective for the observed mid-gap interface states, in line with other recent observations.^{22, 26, 27} Note finally that the FGA conditions chosen here are not optimal for interface state passivation but have been selected to yield the best recombination lifetime for our process conditions.

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At the same time, one should be cautious in drawing too strong quantitative conclusions, as the DLTS and D_it spectra can exhibit quite some device to device scatter, as illustrated by Fig. 5. However, the similarity of both distributions in Figs. 3 and 4 strongly suggests that the same type is of interface traps are being probed, namely associated with the Si/SiO₂ interface. In the case of the Al₂O₃ samples, the interface states are formed at the thin SiO₂ interfacial layer. X-ray Photo-Electron (XPS) spectroscopy revealed no detectable SiO₂ in the as-deposited samples, but after FGA and firing, a regrowth occurs, yielding a thickness of 0.26 and 1.51 nm, respectively. This is also confirmed by Electron Spin Resonance (ESR), showing the presence of ∼10₁₂ cm₋₂ dangling bond centers, typical for the SiO₂/Si interface.

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In summary, it has been shown by DLTS that the density of interface states is strongly reduced after post-Al-metallization FGA or firing of Al/Al₂O₃/p-Si MOS capacitors, while at the same time, the activation energy of the interface states shifts to lower values. Both factors should contribute to the improvement of the surface recombination properties of Al₂O₃ passivated p-type Si.

Acknowledgments