Abstract
The vias between two levels of metal interconnect in a multilevel metal system are filled using either selective or nonselective chemical vapor deposited (CVD) tungsten. Excess tungsten is then removed from the surface of the interlayer dielectric using planarization and etch back which leaves the vias filled with tungsten plugs. The uniformity of the etch‐back process can be effected by "micro‐loading" which causes local accelerated etching of the tungsten in the vias. Other nonuniformities in etch rate, resulting in trenching around the periphery of the tungsten vias, can be caused by contaminants in the CVD reactor chamber which are incorporated in the deposited film. Methods for eliminating such problems and optimizing coverage of the plugs by the overlying metal are described.