E.-G. Jung
ABSTRACT
In this paper, we propose a high performance asynchronous on-chip bus with multiple issue and in-order/out-of-order completion for a Globally Asynchronous Locally Synchronous (GALS) design. The proposed bus implementation can be characterized with distributed and modularized control units based on a layered architecture to support multiple issue and in-order/out-of-order completion. Simulation results reveal that throughputs of asynchronous on-chip buses with multiple issue and in-order/out-of-order completion increases by 31.3% / 34.3%, while power consumption overhead is only 6.76% / 3.98% respectively, compared to a simple asynchronous on-chip bus with only a single issue feature.
- Semiconductor Industry Association, International technology roadmap for semiconductors (ITRS) 2003.Google Scholar
- J. Bainbridge, Asynchronous system-on-chip interconnect. Ph.D. thesis, The University of Manchester, UK, 2000. Google ScholarDigital Library
- E.-G. Jung, B.-S. Choi, and D.-I. Lee High performance asynchronous bus for SoC. In Proc. ISCAS, 2003, V-505-V-508.Google Scholar
- E. Salminen, V. Lahtinen, K. Kuusilinna, and T. Hamalainen Overview of bus-based system-on-chip interconnections. In Proc. ISCAS, 2002, II-372-II-375.Google Scholar
- ARM Corporation, AMBA AXI protocol specification, 2003.Google Scholar
- E.-S.Kim, J.-G. Lee, D.-I. Lee Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis. In Proc. ASYNC, 2000, 104--105. Google ScholarDigital Library
- H. Zimmermann OSI reference model--the ISO model of architecture for open systems interconnection. IEEE Trans. Communications, 28 (Apr. 1980), 425--432.Google ScholarCross Ref
- J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Trans. Info. & Syst., E80-D (Mar. 1997), 315--325.Google Scholar
Index Terms
- High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion
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