- 1 Kaeli I).R., Kirkpatrick S., Ong S., "PC Workload Characterization', Proceedings of the ACM Sigmetrics and I~erlbrmance "89", May 89, pp.220.Google Scholar
- 2 Adams T., Zimmerman R., "An Analysis of 8086 instruction usage in MS DOS programs', Proc. Third Symposium on Architectural Support For Programming l~anguages arid Operating Systems, Boston, 1989, pps.152-161. Google ScholarDigital Library
- 3 Clark I).W., i.evy II., "Measurement and Analysis of Instruction Use in the VAX 11/78{1", Proc. Ninth Symposium o~ Computer Architecture, Austin, Tx., April 1982, pps.9-17. Google ScholarDigital Library
- 4 Grohoski G.F., "Machine Organization of the IBM RIS(~ System/6{)00 processor", IBM Journal of Research and Development, Vol.34, No.l, Jan. 1990, pps.37-58. Google ScholarDigital Library
- 5 Patterson I).A, "Reduced Instruction Set Computers', Communications of the ACM, Vol.28-1, Jan, 1085, pps.8-21. Google ScholarDigital Library
- 6 Ditzel I).R., McLellan I I.R., "Branch Folding in the Crisp Microprocessor: Reducing Branch Delay to Zero," Proc. 14th Ann. Syrup. Computer Arch., 1987, pps.2-9. Google ScholarDigital Library
- 7 Anderson D.W. etal., "'File IBM System/360 Model 91" Machine pllilosophy and instruction handling', IBM Journal of Research and l)evclopment, Jan. 1967, pps.8-24.Google ScholarDigital Library
- 8 Campbell R., "Compiling C for the Reduced Instruction Set Computer", Master's report, EECS, U.fL Berkeley 94721), l)ec. 198(I.Google Scholar
- 9 Sll~ittl J.l~., "A Study of Branch Prediction Strategies', l~roc, i';ightll Sylnposiutn on (.'olnputer Architecture, May 1981, Minneapolis, pps.135-148. Google ScholarDigital Library
- 10 l~ee J., Smith A.J., "Branch Prediction Strategies and Branch "l'arget Buffer l)esign~, Computer 17:1, Jan. 1984, pps.6-22.Google ScholarDigital Library
- 11 Ilolgate R.W., ibbett R.N., "An Analysis of lnslruclion-l:etcl~ing Strategies in Pipelined (2omputers". IEI';E 'l'rans. on Computers. Voi.C-29. No.4, April 198{}, pps. 325-329.Google Scholar
- 12 I luglles J.I:., I.iplay J.S., Rymarczyk J.W., Stone S.E., ~Mtllti-lnslruclion Stream Branch Processing Mect~anism", U.S. Patent 4,200,927, Apr. 29, 1980.Google Scholar
- 13 Lilja D.J., "Reducing the Branch Penalty in Pipelined Processors', IEEE Computer Magazine, July 1988, pps.47-55. Google ScholarDigital Library
- 14 Pomerene J.H., Puzak T.R., Rechtschaffen R.N., Rosenfeld P.L., Sparacio F.J., "Pageable Branch History Table', U.S. Patent 4,679,141, Jul. 7, 1987.Google Scholar
- 15 Smith A.J., "Cache Memories', Computing Surveys, Vol.14 No.3, Sept. 1982. pps.473-530. Google ScholarDigital Library
- 16 SPEC Quarterly Newsletter, System Performance Evaluation Cooperative, 1st Quarter 1990.Google Scholar
- 17 Webb C.F., "Subroutine Call/Return Stack', IBM Tech. Disc. Bullen., Vol.30, No.1 I, April 1988.Google Scholar
Index Terms
- Branch history table prediction of moving target branches due to subroutine returns
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