Febin P. Sunny
Sudeep Pasricha
Skip Abstract Section
Abstract
Domain specific neural network accelerators have garnered attention because of their improved energy efficiency and inference performance compared to CPUs and GPUs. Such accelerators are thus well suited for resource-constrained embedded systems. However, mapping sophisticated neural network models on these accelerators still entails significant energy and memory consumption, along with high inference time overhead. Binarized neural networks (BNNs), which utilize single-bit weights, represent an efficient way to implement and deploy neural network models on accelerators. In this paper, we present a novel optical-domain BNN accelerator, named ROBIN, which intelligently integrates heterogeneous microring resonator optical devices with complementary capabilities to efficiently implement the key functionalities in BNNs. We perform detailed fabrication-process variation analyses at the optical device level, explore efficient corrective tuning for these devices, and integrate circuit-level optimization to counter thermal variations. As a result, our proposed ROBIN architecture possesses the desirable traits of being robust, energy-efficient, low latency, and high throughput, when executing BNN models. Our analysis shows that ROBIN can outperform the best-known optical BNN accelerators and many electronic accelerators. Specifically, our energy-efficient ROBIN design exhibits energy-per-bit values that are ∼4 × lower than electronic BNN accelerators and ∼933 × lower than a recently proposed photonic BNN accelerator, while a performance-efficient ROBIN design shows ∼3 × and ∼25 × better performance than electronic and photonic BNN accelerators, respectively.
- N. P. Jouppi et al. 2017. In-datacenter performance analysis of a tensor processing unit. In ISCA 2017. Google Scholar
Digital Library
- Intel Movidius VPU. 2020. [Online]: https://www.intel.com/content/www/us/en/products/processors/movidius-vpu/movidius-myriad-x.html.Google Scholar
- M. Coubariaux et al. BinaryNet: Training deep neural networks with weights and activations constrained to +1 or -1. arXiv 2016, arXiv:1602.02830.Google Scholar
- I. hubara et al. 2016. Binarized neural networks. In NIPS Dec. 2016. Google ScholarDigital Library
- M. M. Waldrop. 2016. The chips are down for Moore's law. In Nature News 530, 7589 (2016).Google ScholarCross Ref
- S. Pasricha, N. Dutt. 2008. On-chip communication architectures. Morgan Kauffman, ISBN 978-0-12-373892-9, Apr 2008. Google ScholarDigital Library
- A. K. Ziabari et al. 2015. Leveraging silicon-photonic noc for designing scalable GPUs. In ACM ICS 2015. Google ScholarDigital Library
- S. Pasricha and M. Nikdast. 2020. A survey of silicon photonics for energy efficient manycore computing. In IEEE Design and Test 37, 4 (2020).Google Scholar
- D. A. Miller. 2017. Silicon photonics: Meshing optics with applications. In Nature Photonics 11, 7 (2017).Google Scholar
- Y. Shen et al. 2017. Deep learning with coherent nanophotonic circuits. In Nature Photonics 11, 7 (2017).Google Scholar
- P. Pintus et al. 2019. PWM-Driven thermally tunable silicon microring resonators: Design, fabrication, and characterization. In L&P Reviews 13, 9 (2019).Google Scholar
- F. Sunny et al. A survey on silicon photonics for deep learning. arXiv 2021, arXiv:2101.01751 Google ScholarDigital Library
- Z. Zhao et al. 2019. Hardware-software co-design of slimmed optical neural networks. in IEEE/ACM ASPDAC, 2019. Google ScholarDigital Library
- V. Bangari, B. A. Marquez, H. Miller, A. N. Tait, et al. 2020. Digital electronics and analog photonics for convolutional neural networks (DEAP-CNNs). In IEEE JQE 26, 1 (2020).Google Scholar
- W. Liu et al. 2019. HolyLight: A nanophotonic accelerator for deep learning in data centers. In IEEE/ACM DATE 2019.Google ScholarCross Ref
- K. Shiflett, D. Wright, A. Karanth, and A. Louri. 2020. PIXEL: Photonic neural network accelerator. In HPCA 2020.Google Scholar
- A. N. Tait et al. 2017. Neuromorphic photonic networks using silicon photonic weight banks. In Sci. Rep. 7, 1 (2017).Google Scholar
- G. Mourgias-Alexandris et al. 2020. Neuromorphic photonics with coherent linear neurons using dual-IQ modulation cells. In IEEE JLT 38, 4 (2020).Google Scholar
- C. Pask. 1978. Generalized parameters for tunneling ray attenuation in optical fibers. In J. Opt. Soc. Am. 68, 1 (1978).Google ScholarCross Ref
- J. Anderson et al. 2019. Photonic processor for fully discretized neural networks. In IEEE ASAP 2019Google ScholarCross Ref
- F. Zokae et al. 2020. LightBulb: A photonic-nonvolatile-memory-based accelerator for binarized convolutional neural networks. In IEEE/ACM DATE 2020. Google ScholarDigital Library
- A. R. Totovic et al. 2020. Femtojoule per MAC neuromorphic photonics: An energy and technology roadmap. In IEEE Journal of selected topics in Quantum Electronics 26, 5 (Sept.-Oct. 2020), 1–15.Google Scholar
- M. Nikdast et al. 2016. Chip-scale silicon photonic interconnects: A formal study on fabrication non-uniformity. In IEEE JLT, 34, 16 (2016).Google Scholar
- A. Stefan et al. 2016. A hybrid barium titanate–silicon photonics platform for ultraefficient electro-optic tuning. In IEEE JLT 34, 8 (2016).Google Scholar
- Y. Bengio et al. Estimating or propagating gradients through stochastic neurons for conditional computation. arXiv,2013, arXiv:13126199.Google Scholar
- A. Stefan et al. 2016. A hybrid barium titanate–silicon photonics platform for ultraefficient electro-optic tuning. In IEEE JLT 34, 8 (2016).Google Scholar
- P. Pintus et al. 2019. PWM-Driven thermally tunable silicon microring resonators: Design, fabrication, and characterization. In L&P Reviews 13, 9 (2019).Google Scholar
- L. Lu et al. 2019. Silicon non-blocking 4 × 4 optical switch chip integrated with both thermal and electro-optic tuners. In IEEE Photonics 11, 6 2019.Google Scholar
- M. Milanizadeh et al. 2019. Canceling thermal cross-talk effects in photonic integrated circuits. In IEEE JLT 37, 4 (2019).Google Scholar
- Lumerical Solutions Inc. Lumerical MODE. [Online]. Available: http://www.lumerical.com/tcad-products/mode/.Google Scholar
- Y. Liu et al. 2019. Adiabatic and ultracompact waveguide tapers based on digital metamaterials. In IEEE Journal of Selected Topics in Quantum Electronics 25, 3 (May-June 2019), 1–6.Google ScholarCross Ref
- L. Duong et al. 2014. A case study of signal-to-noise ratio in ring based optical networks-on-chip. IEEE Design & Test 31, 5 (2014).Google Scholar
- W. Bogaerts et al. 2012. Silicon microring resonators. In L&P Reviews 6, 1 (2012).Google Scholar
- Z. Su, E. S. Hosseini, E. Timurdogan, J. Sun, G. Leake, D. D. Coolbaugh, and M. R. Watts. 2014. Reduced wafer-scale frequency variation in adiabatic microring resonators. In OFC, 2014.Google ScholarCross Ref
- Q. Xu, D. Fattal, and R. G. Beausoleil. 2008. Silicon microring resonators with 1.5-μm radius. In Optics express 16, 6 (2008), 4309–4315.Google Scholar
- B. E. Little, S. T. Chu, H. A. Haus, J. Foresi, and J.-P. Laine. 1997. Microring resonator channel dropping filters. In IEEE JLT 15, 6 (1997), 998–1005.Google Scholar
- J. Xia, A. Bianco, E. Bonetto, and R. Gaudino. 2014. On the design of microring resonator devices for switching applications in flexible-grid networks. In IEEE International Conference on Communications (ICC) 2014, pp. 3371–3376.Google Scholar
- A. Mirza, F. Sunny, S. Pasricha, and M. Nikdast. 2020. Silicon photonic microring resonators: Design optimization under fabrication non-uniformity. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference and Exhibition, Grenoble, France 2020, pp. 484–489. Google ScholarDigital Library
- T. Chen et al. 2014. DianNao: A small-footprint high-throughput accelerator for ubiquitous machine-learning. In ACM ASPLOS 2014. Google ScholarDigital Library
- M. Bahadori et al. 2018. Design space exploration of microring resonators in silicon photonic interconnects: Impact of the ring curvature. IEEE JLT 36 13 (July 2018), 2767–2782.Google Scholar
- Y. LeCun et al. 1998. Gradient-based learning applied to document recognition. In Proceedings of the IEEE 1998.Google ScholarCross Ref
- QKeras, https://github.com/google/qkeras.Google Scholar
- M. Courbariaux et al. 2015. BinaryConnect: Training deep neural networks with binary weights during propagation. In NIPS 2015 Google ScholarDigital Library
- Z. Ruan et al. 2020. Efficient hybrid integration of long-wavelength VCSELs on silicon photonic circuits. IEEE JLT 38, 18 (2020).Google Scholar
- A. D. Güngördü, G. Dündar, and M. B. Yelten. 2020. A high performance TIA design in 40 nm CMOS. In IEEE ISCAS 2020.Google Scholar
- B. Wang et al. 2020. A low-voltage Si-Ge avalanche photodiode for high-speed and energy efficient silicon photonic links. In IEEE JLT 38, 12 (2020).Google Scholar
- B. Wu, S. Zhu, B. We, and Y. Chiu. 2016. A 24.7 mW 65 nm CMOS SARassisted CT modulator with second-order noise coupling achieving 45 MHz bandwidth and 75.3 dB SNDR. In IEEE J. Solid-State Circuits 51, 12 (Dec. 2016), 2893–2905.Google ScholarCross Ref
- J. Shen et al. 2018. A 16-bit 16-MS/s SAR ADC with on-chip calibration in 55-nm CMOS. In IEEE J. Solid-State Circuits 53 4 (April 2018), 1149–1160.Google ScholarCross Ref
- L. H. Frandsen et al. 2004. Ultralow-loss 3-dB photonic crystal waveguide splitter. In Optics letters 29, 14 (2004).Google Scholar
- Y. Tu et al. 2019. High-Efficiency ultra-broadband multi-tip edge couplers for integration of distributed feedback laser with silicon-on-insulator waveguide In IEEE Photonic Journal 11, 4 (2019).Google Scholar
- S. Bahirat and S. Pasricha. 2011. OPAL: A multi-layer hybrid photonic NoC for 3D ICs. In IEEE/ACM ASPDAC 2011. Google ScholarDigital Library
- H. Jayatileka et al. 2015. Crosstalk limitations of microring-resonator based WDM demultiplexers on SOI. In OIC 2015.Google ScholarCross Ref
- E. Timurdogan et al. 2013. Vertical junction silicon microdisk modulator with integrated thermal tuner. In CLEO:Science and Innovations OSA 2013.Google ScholarCross Ref
- E. Qin et al. 2020. SIGMA: A Sparse and irregular GEMM Accelerator with flexible interconnects for DNN training. In IEEE HPCA 2020.Google ScholarCross Ref
- S. Cass. 2019. Taking AI to the edge: Google's TPU now comes in a maker-friendly package. In IEEE Spectrum 56, 5 (May 2019), 16–17.Google ScholarCross Ref
- T. Luo et al. 2017. DaDianNao: A neural network supercomputer. In IEEE Transactions on Computers 66, 1 (1 Jan. 2017), 73–88. Google ScholarDigital Library
- A. Aimar et al. 2016. NullHop: A flexible convolutional neural network accelerator based on sparse representations of feature maps. In IEEE Trans. Neural Netw. Learn. Syst. 30, 3 (March 2016), 644–656.Google Scholar
- P. Guo et al. 2018. FBNA: A fully binarized neural network accelerator. International Conference on Field Programmable Logic and Applications 2018.Google ScholarCross Ref
- Y. Umuroglu et al. 2017. FINN: A framework for fast, scalable binarized neural network inference. In ACM/SIGDA FPGA 2017. Google ScholarDigital Library
- M. Capra et al. 2020. An updated survey of efficient hardware architectures for accelerating deep convolutional neural networks. In Future Internet 2020.Google Scholar
Index Terms
- ROBIN: A Robust Optical Binary Neural Network Accelerator
Recommendations
GHOST: A Graph Neural Network Accelerator using Silicon Photonics
Special Issue ESWEEK 2023Graph neural networks (GNNs) have emerged as a powerful approach for modelling and learning from graph-structured data. Multiple fields have since benefitted enormously from the capabilities of GNNs, such as recommendation systems, social network analysis,...
Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA
FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysBinarized Neural Network (BNN) removes bitwidth redundancy in classical CNN by using a single bit (-1/+1) for network parameters and intermediate representations, which has greatly reduced the off-chip data transfer and storage overhead. However, a ...
Efficient binary 3D convolutional neural network and hardware accelerator
AbstractThe three-dimensional convolutional neural networks have abundant parameters and computational costs. It is urgent to compress the three-dimensional convolutional neural network. In this paper, an efficient and simple binary three-dimensional ...
Comments