Abstract
Resistive Random Access Memory (ReRAM), a form of non-volatile memory, has been proposed as a Flash memory replacement. In addition, novel circuit architectures have been proposed that rely on newly discovered or predicted behavior of ReRAM. One such architecture is the memristive Dynamic Adaptive Neural Network Array, developed to emulate the functionality of a biological neuron system. We demonstrated ReRAM devices that show a synaptic tendency by changing their resistance in an analog fashion. The CMOS compatible nanoscale ReRAM devices shown are based on an HfO2 switching layer that sits on a tungsten electrode and is covered by a titanium oxygen scavenger layer and a titanium nitride top electrode. In this work, we showed devices exceeding endurance values of 10B cycles with a discrete Roff/Ron ratio of 15. Multi-level states were achieved by using consecutive ultra-short 5/1.5 ns pulses during the reset operation. A neural network simulation was performed in which the synaptic weights were perturbed with the ReRAM variability, which was extracted from two different characterization methods: (1) via direct write, and (2) via a write/read verification approach during the reset operation. A substantial improvement of the neural network fitness was demonstrated when using the write/read verification approach.
- D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams. 2008. The missing memristor found. Nature 453 (2008), 80--83.Google ScholarCross Ref
- D. S. Jeong, H. Schroeder, and R. Waser. 2007. Coexistence of bipolar and unipolar resistive switching behaviors in a Pt TiO2 Pt stack. Electrochem. Solid-State Lett. 10, 8 (2007).Google ScholarCross Ref
- M. N. Kozicki, M. Yun, S. J. Yang, J. P. Aberouette, and J. P. Bird. 2000. Nanoscale effects in devices based on chalcogenide solid solutions. Superlatt. Microstruct. 27, 5 (2000), 485--488.Google ScholarCross Ref
- T. Fujii, M. Kawasaki, A. Sawa, H. Akoh, Y. Kawazoe, and Y. Tokura. 2005. Hysteretic current—Voltage characteristics and resistance switching at an epitaxial oxide Schottky junction SrRuO[sub 3]∕SrTi[sub 0.99]Nb[sub 0.01]O[sub 3]. Appl. Phys. Lett. 86, 1 (2005), 012107.Google ScholarCross Ref
- A. Beck, J. G. Bednorz, C. Gerber, C. Rossel, and D. Widmer, 2000. Reproducible switching effect in thin oxide films for memory applications. Appl. Phys. Lett. 77, 1 (2000), 139Google ScholarCross Ref
- L. Chua. 1971. Memristor—The missing circuit element. IEEE Trans. Circ. Theory 18, 5 (1971). 507--519.Google ScholarCross Ref
- D.-J. Seong et al. 2013. Highly reliable ReRAM technology with encapsulation process for 20nm and beyond. In Proceedings of the 5th IEEE International Memory Workshop. 42--43.Google ScholarCross Ref
- Y. Hayakawa et al. 2015. Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application. In Proceedings of the Symposium on VLSI Technology. T14--T15.Google Scholar
- R. Waser, R. Dittmann, G. Staikov, and K. Szot. 2009. Redox-based resistive switching memories—Nanoionic mechanisms, prospects, and challenges. Adv. Mater. 21, 25--26 (July 2009), 2632--2663.Google ScholarCross Ref
- S. Menzel, M. Waters, A. Marchewka, U. Böttger, R. Dittmann, and R. Waser. 2011. Origin of the Ultra-nonlinear switching kinetics in oxide-based resistive switches. Adv. Funct. Mater. 21, 23 (Dec. 2011), 4487--4492.Google ScholarCross Ref
- D. Kuzum, R. G. D. Jeyasingh, B. Lee, and H.-S. P. Wong. 2012. Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing. Nano Lett, 125 (May 2012), 2179--86.Google Scholar
- G. W. Burr et al. 2015. Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses) using phase-change memory as the synaptic weight element. IEEE Trans. Electron. Dev. 62 11 (2015), 3498--3507.Google Scholar
- K. Beckmann, H. Manem, and N. C. Cady. 2017. Performance enhancement of a time-delay PUF design by utilizing integrated nanoscale ReRAM devices. IEEE Trans. Emerg. Top. Comput. 5, 3 (July 2017), 304--316.Google Scholar
- J. Rajendran, H. Manem, R. Karri, and G. S. Rose. 2012. An energy-efficient memristive threshold logic circuit. IEEE Trans. Comput. 61, 4 (Apr. 2012), 474--487.Google ScholarDigital Library
- Z. Alamgir, K. Beckmann, N. Cady, A. Velasquez, and S. K. Jha. 2016. Flow-based computing on nanoscale crossbars: Design and implementation of full adders. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’16). 1870--1873.Google Scholar
- M. Hu, H. Li, Y. Chen, Q. Wu, G. S. Rose, and R. W. Linderman. 2014. Memristor crossbar-based neuromorphic computing system: A case study. IEEE Trans. Neural Netw. Learn. Syst. 25, 10 (Oct. 2014), 1864--1878.Google ScholarCross Ref
- G. S. Rose, N. McDonald, L.-K. Yan, and B. Wysocki. 2013. A write-time based memristive PUF for hardware security applications. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’13). 830--833.Google Scholar
- H. Manem, K. Beckmann, M. Xu, R. Carroll, R. Geer, and N. C. Cady. 2015. An extendable multi-purpose 3D neuromorphic fabric using nanoscale memristors. In Proceedings of the IEEE Symposium on Computational Intelligence for Security and Defense Applications (CISDA’15). 1--8.Google Scholar
- T. E. Potok et al. 2016. A study of complex deep learning networks on high performance, neuromorphic, and quantum computers. In Proceedings of the 2nd Workshop on Machine Learning in HPC Environments (MLHPC’16). 47--55.Google ScholarCross Ref
- J. Schemmel, D. Briiderle, A. Griibl, M. Hock, K. Meier, and S. Millner. 2010. A wafer-scale neuromorphic hardware system for large-scale neural modeling. In Proceedings of IEEE International Symposium on Circuits and Systems. 1947--1950.Google Scholar
- A. Kalampokis, C. Kotsavasiloglou, P. Argyrakis, and S. Baloyannis. 2003. Robustness in biological neural networks. Phys. A Stat. Mech. Appl. 317, 3--4 (Jan. 2003), 581--590.Google ScholarCross Ref
- X. Liu et al. 2016. Harmonica: A framework of heterogeneous computing systems with memristor-based neuromorphic computing accelerators. IEEE Trans. Circ. Syst. I Regul. Pap. 63, 5 (May 2016), 617--628.Google ScholarCross Ref
- G. Indiveri, B. Linares-Barranco, R. Legenstein, G. Deligeorgis, and T. Prodromakis. 2013. Integration of nanoscale memristor synapses in neuromorphic computing architectures. Nanotechnology. 24 38 (Sept. 2013), 384010.Google Scholar
- R. J. Vogelstein, U. Mallik, J. T. Vogelstein, and G. Cauwenberghs. 2007. Dynamically reconfigurable silicon array of spiking neurons with conductance-based synapses. IEEE Trans. Neural Netw. 18, 1 (Jan. 2007), 253--265.Google ScholarDigital Library
- S. Kim et al. 2015. NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning. In Proceedings of the International Electron Devices Meeting (IEDM’15).Google ScholarCross Ref
- M. Suri et al. 2012. Interface engineering of PCM for improved synaptic performance in neuromorphic systems. In Proceedings of the 4th IEEE International Memory Workshop (IMW’12). 1--4.Google ScholarCross Ref
- G. W. Burr et al. 2015. Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: Comparative performance analysis (accuracy, speed, and power). In Proceedings of the IEEE International Electron Devices Meeting (IEDM’15). 4.4.1--4.4.4.Google ScholarCross Ref
- R. B. Jacobs-Gedrim et al. 2017. Impact of linearity and write noise of analog resistive memory devices in a neural algorithm accelerator. In Proceedings of the IEEE International Conference on Rebooting Computing (ICRC’17). 1--10.Google Scholar
- S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu. Nanoscale memristor device as synapse in neuromorphic systems. Nano Lett. 10, 4 (Apr. 2010), 1297--301.Google Scholar
- J.-W. Jang, S. Park, Y.-H. Jeong, and H. Hwang. 2014. ReRAM-based synaptic device for neuromorphic computing. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’14). 1054--1057.Google Scholar
- J. Woo, A. Padovani, K. Moon, M. Kwak, L. Larcher, and H. Hwang. 2017. Linking conductive filament properties and evolution to synaptic behavior of RRAM devices for neuromorphic applications. IEEE Electron. Dev. Lett. 38, 9 (Sept. 2017), 1220--1223.Google ScholarCross Ref
- S. Yu, B. Gao, Z. Fang, H. Yu, J. Kang, and H.-S. P. Wong. 2012. A neuromorphic visual system using RRAM synaptic devices with Sub-pJ energy and tolerance to variability: Experimental characterization and large-scale modeling. In Proceedings of the International Electron Devices Meeting. 10.4.1--10.4.4.Google ScholarCross Ref
- Z. Alamgir, K. Beckmann, J. Holt, and N. C. Cady. 2017. Pulse width and height modulation for multi-level resistance in bi-layer TaOx based RRAM. Appl. Phys. Lett. 111, 6 (Aug. 2017).Google ScholarCross Ref
- M. J. Marinella et al. 2018. Multiscale co-design analysis of energy, latency, area, and accuracy of a ReRAM analog neural training accelerator. IEEE J. Emerg. Sel. Top. Circ. Syst. 8, 1 (Mar. 2018), 86--101.Google Scholar
- Q. Xia and J. J. Yang. 2019. Memristive crossbar arrays for brain-inspired computing. Nature Mat. 18, 4 (Apr 2019), 309--323.Google Scholar
- M. Liehr et al. 2019. Fabrication and performance of hybrid RERAM-CMOS circuit elements for dynamic neural networks. In Proceedings of the ACM International Conference.Google ScholarDigital Library
- N. C. Cady, K. Beckmann, H. Manem, M. E. Dean, G. Rose, and J. E. Van Nostrand. 2016. Towards memristive dynamic adaptive neural network arrays. In Proceedings of the Government Microcircuit Applications and Critical Technology Conference (GOMACTech’16). 1--4.Google Scholar
- A. Disney, J. Reynolds, C. D. Schuman, A. Klibisz, A. Young, and J. S. Plank. 2016. DANNA: A neuromorphic software ecosystem. Biol. Inspired Cogn. Archit. 17 (2016), 49--56.Google ScholarCross Ref
- C. D. Schuman, A. Disney, and J. Reynolds. 2015. Dynamic adaptive neural network arrays: A Neuromorphic Architecture. In Proceedings of the Workshop on Machine Learning in High-Performance Computing Environments (MLHPC’15). 1--4.Google Scholar
- Q. Liu et al. 2012. Resistive switching: Real-time observation on dynamic growth/dissolution of conductive filaments in oxide-electrolyte-based ReRAM. Adv. Mater. 24 (2012), 1844--1849.Google ScholarCross Ref
- A. Marchewka et al. 2016. Nanoionic resistive switching memories: On the physical nature of the dynamic reset process. Adv. Electron. Mater. 2, 1 (Jan. 2016), 1--13.Google Scholar
- F. Cüppers et al. 2019. Exploiting the switching dynamics of HfO 2-based ReRAM devices for reliable analog memristive behavior. APL Mater. 7, 9 (2019), 091105.Google ScholarCross Ref
- C. D. Schuman, J. D. Birdwell, and M. Dean. 2014. Neuroscience-inspired dynamic architectures. In Proceedings of the Biomedical Science & Engineering Conference (BSEC’14). 1--4.Google Scholar
- C. D. Schuman and J. D. Birdwell. 2013. Variable structure dynamic artificial neural networks. Biol. Inspired Cogn. Archit. 6 (Oct. 2013), 126--130.Google Scholar
- T. Dalgaty et al. 2019. Hybrid CMOS-RRAM neurons with intrinsic plasticity. In Proceedings of the IEEE International Symposium on Circuits and Systems.Google ScholarCross Ref
Index Terms
- Towards Synaptic Behavior of Nanoscale ReRAM Devices for Neuromorphic Computing Applications
Recommendations
Fabrication and Performance of Hybrid ReRAM-CMOS Circuit Elements for Dynamic Neural Networks
ICONS '19: Proceedings of the International Conference on Neuromorphic SystemsIn neuromorphic applications, resistive memory solutions (implemented as Resistive Random Access Memory or ReRAM) have significant potential in emulating the desired two-terminal synaptic functionality of real synapses. One of the unique features for the ...
Adaptive programming in multi-level cell ReRAM
AbstractResistive memory (ReRAM) is an attractive technology to replace Flash technology and/or serve as a new memory tier. When a fixed programming voltage is applied to the resistive cell (memristor), its resistance changes logarithmically ...
Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design
DSD '13: Proceedings of the 2013 Euromicro Conference on Digital System DesignRecently, multiple non-volatile emerging memories (NVMs) have been proposed and show promising properties to replace SRAM-based memories in future SoCs. However, these new emerging memories, such as STT-MRAM and ReRAM, provide new challenges for the ...
Comments