ABSTRACT
In this paper, we propose a reconfigurable design of the Advanced Encryption Standard capable of adapting at runtime to the requirements of the target application. Reconfiguration is achieved by activating only a specific subset of all the instantiated processing elements. Further, we explore the effectiveness of power gating and clock gating methodologies to minimize the energy consumption of the processing elements not involved in computation.
- S. Banik et al. Exploring Energy Efficiency of Lightweight Block ciphers. SAC, 2015.Google Scholar
- S. Banik et al. Exploring the energy consumption of lightweight blockciphers in fpga. Cn. on Reconfigurable Computing and FPGAs, 2015.Google ScholarCross Ref
- L. Batina et al. Dietary recommendations for lightweight block ciphers: Power, energy and area analysis of recently developed architectures. Work. on Radio Frequency Identification - Security and Privacy Issues, pages 103--112, 2013.Google ScholarCross Ref
- G. Bertoni et al. Power-efficient ASIC synthesis of cryptographic sboxes. ACM GLSVLSI, page 281. Google ScholarDigital Library
- D. Canright. A very compact S-Box for AES. CHES, volume 3659, pages 441--455. 2005. Google ScholarDigital Library
- N. Carta et al. A coarse-grained reconfigurable approach for low-power spike sorting architectures. Cn. on Neural Engineering, 2013.Google ScholarCross Ref
- K. Compton et al. Reconfigurable computing: A survey of systems and software. ACM Comput. Surv., 34(2):171--210, June 2002. Google ScholarDigital Library
- J. Daemen et al. The Design of Rijndael: AES - The Advanced Encryption Standard. Information Security and Cryptography. 2002. Google ScholarCross Ref
- M. Feldhofer et al. Aes implementation on a grain of sand. IEE Proc. of Information Security, 152(1):13--20, 2005.Google ScholarCross Ref
- T. Good et al. 692-nW Advanced Encryption Standard (AES) on a 0.13μm. IEEE Trans. on VLSI Systems, (99):1. Google ScholarDigital Library
- C. Hocquet et al. Harvesting the potential of nano-cmos for lightweight cryptography: an ultra-low-voltage 65 nm aes coprocessor for passive rfid tags. J. of Cryptographic Engineering, 1(1):79--86, 2011.Google ScholarCross Ref
- W. Hussain et al. Designing fast fourier transform accelerators for orthogonal frequency-division multiplexing systems. J. Signal Process. Syst., 69(2). Google ScholarDigital Library
- S. Kerckhof at al. Towards green cryptography: A comparison of lightweight ciphers from the energy viewpoint. CHES, pages 390--407, 2012. Google ScholarDigital Library
- N. Mentens et al. A systematic evaluation of compact hardware implementations for the Rijndael S-box. CT-RSA, pages 323--333, 2005. Google ScholarDigital Library
- A. Moradi et al. Pushing the limits: A very compact and a threshold implementation of AES. Cn. on the Theory and Appl. of Cryptographic Techniques, 2011. Google ScholarDigital Library
- S. Morioka et al. An optimized s-box circuit architecture for low power AES design. Work. on Cryptographic Hardware and Embedded Systems, 2002. Google ScholarDigital Library
- F. Palumbo et al. The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms. J. of real-time image processing, 9(1):233--249, 2014. Google ScholarDigital Library
- F. Palumbo et al. Power-awarness in coarse-grained reconfigurable multi-functional architectures: a dataflow based strategy. J. of Signal Processing Systems, pages 1--26, 2016.Google Scholar
- Y. Park et al. Efficient performance scaling of future cgras for mobile applications. Cn. on Field-Programmable Technology, 2012.Google ScholarCross Ref
- A. Satoh et al. A compact rijndael hardware architecture with s-box optimization. Cn. on the Theory and Appl. of Cryptology and Information Security, 2001. Google ScholarDigital Library
Recommendations
Automated power gating methodology for dataflow-based reconfigurable systems
CF '15: Proceedings of the 12th ACM International Conference on Computing FrontiersModern embedded systems designers are required to implement efficient multi-functional applications, over portable platforms under strong energy and resources constraints. Automatic tools may help them in challenging such a complex scenario: to develop ...
A novel AES-256 implementation on FPGA using co-processor based architecture
ICACCI '12: Proceedings of the International Conference on Advances in Computing, Communications and InformaticsEfficient hardware architecture for cryptographic algorithms are of utmost need for implementing secured data communication in embedded applications. The hardware implementation of the algorithms though provides less flexibility, but are faster and ...
Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating
Power gating is a widely used leakage power saving strategy in modern chip designs. However, power gating introduces unique power integrity issues and trade-offs between switching and rush current (wake-up) supply noises. At the same time, the amount of ...
Comments