Eric Sprangle
ABSTRACT
Deeply pipelined, superscalar processors require accurate branch prediction to achieve high performance. Two-level branch predictors have been shown to achieve high prediction accuracy. It has also been shown that branch interference is a major contributor to the number of branches mispredicted by two-level predictors.This paper presents a new method to reduce the interference problem called agree prediction, which reduces the chance that two branches aliasing the same PHT entry will interfere negatively. We evaluate the performance of this scheme using full traces (both user and supervisor) of the SPECint95 benchmarks. The result is a reduction in the misprediction rate of gcc ranging from 8.62% with a 64K-entry PHT up to 33.3% with a 1K-entry PHT.
- 1.B. Calder and D. Grunwald, "Fast and Accurate Instruction Fetch and Branch Prediction", Proceedings of the 21st International Symposium on Computer Architecture, (April 1994), pp. 2-11. Google Scholar
Digital Library
- 2.S. McFarling and J. Hennessy, "Reducing the Cost of Branches", Proceedings of the 13th International Symposium on Computer Architecture, (1986), pp. 396-403. Google ScholarDigital Library
- 3.J. A. Fisher and S. M. Freudenberfer, "Predicting Conditional Branch Directions from Previous Runs of a Pro. gram", Proceedings 5th Annual International Conference on Architectural Support for Programming Languages and Operating Systems, (October 1992). Google ScholarDigital Library
- 4.T-Y. Yeh and Y. N. Part, "Two-Level Adaptive Training Branch Prediction", 24th ACM/IEEE International Symposium on Microarchitecture, (November 1991), pp, 51-61. Google ScholarDigital Library
- 5.T-Y. Yeh and Y. N. Part, "A Comprehensive Instruction Fetch Mechanism for Processor Supporting Speculative Execution", 25th ACM/IEEE International Symposium on Microarchitecture, (December 1992), pp. 129-139. Google ScholarDigital Library
- 6.B. Calder, D. Grunwald, and J. Emer, "A System Level Perspective on Branch Architecture Performance," 28th ACM}IEEE International Symposium on Microarchitccture, (November 1995). Google ScholarDigital Library
- 7.A. R. Talcott, M. Nemirovsky, and R. C. Wood. "The Influence of Branch Prediction Table Interference on Branch Prediction Scheme Performance", International Conference on Parallel Architectures and Compilation Techniques, (1995). Google ScholarDigital Library
- 8.C. Young, N. Gloy, and M. D. Smith, "A Comparative Analysis of Schemes for Correlated Branch Prediction", Proceedings of the 22nd Annual International Symposium on Computer Architecture, (1995), pp. 276-286. Google ScholarDigital Library
- 9.S. McFarling, "Combining Branch Predictors", Technical Report TN-36, Digital Western Research Laboratory, (June 1993).Google Scholar
- 10.P-Y. Chang, M. Evers, and Y.N. Part, "Improving Branch Prediction Accuracy by Reducing Pattern History Table Interference", International Conference on Parallel Architectures and Compilation Techniques, (October 1996). Google ScholarDigital Library
Index Terms
- The agree predictor: a mechanism for reducing negative branch history interference
Recommendations
The agree predictor: a mechanism for reducing negative branch history interference
Special Issue: Proceedings of the 24th annual international symposium on Computer architecture (ISCA '97)Deeply pipelined, superscalar processors require accurate branch prediction to achieve high performance. Two-level branch predictors have been shown to achieve high prediction accuracy. It has also been shown that branch interference is a major ...
Branch Classification: A New Mechanism for Improving Branch Predictor Performance
There is wide agreement that one of the most significant impediments to the performance of current and future pipelined superscalar processors is the presence of conditional branches in the instruction stream. Speculative execution is one solution to ...
Comments