skip to main content
article
Free Access

Optimal wiresizing for interconnects with multiple sources

Published:01 October 1996Publication History
Skip Abstract Section

Abstract

In this paper, we study the optimal wiresizing problem for nets with multiple sources under the RC tree model and the Elmore delay model. We decompose the routing tree for a multisource net into the source subtree (SST) and a set of loading subtrees (LSTs), and show that the optimal wiresizing solution satisfies a number of interesting properties, including: LST separability, the LST monotone property, the SST local monotone property, and the dominance property. Furthermore, we study the optimal wiresizing problem using a variable segment-division rather than an a priori fixed segment-division as in all previous works and reveal the bundled refinement property. These properties lead to efficient algorithms to compute the optimal solutions. We have tested our algorithm on nets extracted from the multilayer layout for a high-performance Intel microprocessor. Accurate SPICE simulation shows that our methods reduce the average delay by up to 23.5% and the maximum delay by up to 37.8%, respectively, for the submicron CMOS technology when compared to the minimal wire width solution. In addition, the algorithm based on the variable segment-division yields a speedup of over 100× time and does not lose any accuracy, when compared with the algorithm based on the a priori fixed segment-division.

References

  1. ALPERT, C. J., Hu, T. C., HUANG, J. H., AND KAHNG, A.B. 1993. A direct combination of the Prim and Dijkstra constructions for improved performance-driven routing. In Proceedings of the IEEE International Symposium on Circuits and Systems, (Chicago, IL, May), 1869- 1872.Google ScholarGoogle Scholar
  2. BOESE, K. D., KAHNG, A. B., AND ROBINS, G. 1993. High-performance routing trees with identified critical sinks. In Proceedings of the ACM/IEEE Design Automation Conference, (Dallas, TX, June) 182-187. Google ScholarGoogle Scholar
  3. CHAN, H. 1995. Private communication.Google ScholarGoogle Scholar
  4. CHEN, C. P., CHANG, Y. W., AND WONG, D.F. 1996a. Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation. In Proceedings of the ACM/IEEE Design Automation Conference (Las Vegas, NV, June) 405-408. Google ScholarGoogle Scholar
  5. CHEN, C. P., CHEN, Y. P., AND WONG, D.F. 1996b. Optimal wire-sizing formula under the Elmore delay model. In Proceedings of the ACM/IEEE Design Automation Conference, (Las Vegas, NV, June) 487-490. Google ScholarGoogle Scholar
  6. CONG, J. AND HE, L. 1995a. Optimal wiresizing for interconnects with multiple sources. In Proceedings of the IEEE International Conference on Computer-Aided Design (San Jose, CA, Nov.). Google ScholarGoogle Scholar
  7. CONG, J. AND HE, L. 1995b. Optimal wiresizing for interconnects with multiple sources. UCLA Computer Science, Tech. Rep. 95-00031, Aug.Google ScholarGoogle Scholar
  8. CONG, J. AND HE, L. 1995c. Simultaneous transistor and interconnect sizing based on the general dominance property. UCLA Computer Science, Tech. Rep. 95-00046 (Dec.).Google ScholarGoogle Scholar
  9. CONG, g. AND HE, L. 1996. An efficient approach to simultaneous transistor and interconnect sizing. In Proceedings of the IEEE International Conference on Computer-Aided Design (San Jose, CA, Nov.) (to appear). Google ScholarGoogle Scholar
  10. CONG, J. AND KOH, C.-K. 1994. Simultaneous driver and wire sizing for performance and power optimization. IEEE Trans. VLSI 2, 4 (Dec.), 408-423. Google ScholarGoogle Scholar
  11. CONG, J. AND LEUNG, K. S. 1993. Optimal wiresizing under the distributed Elmore delay model. In Proceedings of the IEEE International Conference on Computer-Aided Design, (San Jose, CA, Nov.) 634-639. Google ScholarGoogle Scholar
  12. CONG, J. AND LEUNG, K. S. 1995. Optimal wiresizing under the distributed Elmore delay model. IEEE Trans. CAD 14, 3 (March), 321-336. Google ScholarGoogle Scholar
  13. CONG, g. AND MADDEN, P.H. 1995. Performance-driven routing with multiple sources. In Proceedings of the IEEE International Symposium on Circuits and Systems. (Seattle, WA, April), 203-206.Google ScholarGoogle Scholar
  14. CONG, J., KAHNG, A. B., ROBINS, G., SARRAFZADEH, M., AND WONG, C.K. 1992. Provably good performance-driven global routing. IEEE Trans. CAD 11, 6 (June), 739-752.Google ScholarGoogle Scholar
  15. CONG, J., LEUNG, K. S., AND ZHOU, D. 1993. Performance-driven interconnect design based on distributed RC delay model. In Proceedings of the ACM/IEEE Design Automation Conference (Dallas, TX, June) 606-611. Google ScholarGoogle Scholar
  16. ELMORE, W. C. 1948. The transient response of damped linear network with particular regard to wideband amplifier. J. Appl. Phys. 19, 55-63.Google ScholarGoogle Scholar
  17. FISHBURN, g. P. AND DUNLOP, A.E. 1985. TILOS: A posynomial programming approach to transistor sizing. In Proceedings of the IEEE International Conference on Computer-Aided Design, (San Jose, CA, Nov.) 326-328.Google ScholarGoogle Scholar
  18. VAN GINNEKEN, L. P. P. P. 1990. Buffer placement in distributed RC-tree networks for minimal Elmore delay. In Proceedings of the International Symposium on Circuits and Systems (New Orleans, LA, May), 865-868.Google ScholarGoogle Scholar
  19. HODES, T. D., MCCOY, B. A., AND ROBINS, G. 1994. Dynamically-wiresized Elmore-based routing constructions. In Proceedings of the International Symposium on Circuits and Systems (London, England, May), 463-466.Google ScholarGoogle Scholar
  20. HONG, X., XUE, T., KUH, E. S., CHENG, C. K., AND HUANG, J. 1993. Performance-driven Steiner tree algorithms for global routing. In Proceedings of the ACM/IEEE Design Automation Conference, 177-181. Google ScholarGoogle Scholar
  21. KAHNG, A. B. AND ROBINS, G. 1992. A new class ofiterative Steiner tree heuristics with good performance. In Proceedings of the IEEE International Conference on Computer-Aided Design (San Jose, CA, Nov.), 893-902.Google ScholarGoogle Scholar
  22. LILLIS, J., CHENG, C. K., AND LIN, T. T.Y. 1995. Optimal wire sizing and buffer insertion for low power and a generalized delay model. In Proceedings of the IEEE International Conference on Computer-Aided Design (San Jose, CA, Nov.), 138-143. Google ScholarGoogle Scholar
  23. LILLIS, J., CHENG, C. K., LIN, T. T. Y., AND HO, C.Y. 1996. New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing. In Proceedings of the ACM/IEEE Design Automation Conference (Las Vegas, NV, June), 395-400. Google ScholarGoogle Scholar
  24. McCoY, B. A. AND ROBINS, G. 1994. Non-tree routing. In Proceedings of the International European Design and Test Conference Symposium on Circuits and Systems (Paris, Feb.), 430-434.Google ScholarGoogle Scholar
  25. MCNC DESIGNERS' MANUAL. North Carolina Microelectronic Center.Google ScholarGoogle Scholar
  26. MENEZES, N., BALDICK, R., AND PILEGGI, L.T. 1995. A sequential quadratic programming approach to concurrent gate and wire sizing. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, (San Jose, CA, Nov.) 144-151. Google ScholarGoogle Scholar
  27. MENEZES, N., PULLELA, S., DARTU, F., AND PILLAGE, L.T. 1994. RC interconnect synthesis--a moment fitting approach. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, (San Jose, CA, Nov.) 418-425. Google ScholarGoogle Scholar
  28. OKAMOTO, T. AND CONG, J. 1996. Buffered Steiner tree construction with wire sizing for interconnect layout optimization. In Proceedings of the IEEE International Conference on Computer-Aided Design (San Jose, CA, Nov.). Google ScholarGoogle Scholar
  29. RUBINSTEIN, J., PENFIELD, P., AND HOROWITZ, M.A. 1983. Signal delay in RC tree networks. IEEE Trans. CAD 2, 3, 202-211.Google ScholarGoogle Scholar
  30. SANCHETI, P. K. AND SAPATNEKAR, S.S. 1994. Interconnect design using convex optimization. In Proceedings of the IEEE Custom Integrated Circuits Conference, (San Diego, CA, May) 549-552.Google ScholarGoogle Scholar
  31. SAPATNEKAR, S. S. 1994. RC interconnect optimization under the Elmore delay model. In Proceedings of the ACM/IEEE Design Automation Conference, (San Diego, CA, June) 387-391. Google ScholarGoogle Scholar
  32. XUE, T. AND KUH, E.S. 1995. Post routing performance optimization via multi-link insertion and non-uniform wiresizing. In Proceedings of the IEEE International Conference on Computer-Aided Design, (San Jose, CA, Nov.) 575-580. Google ScholarGoogle Scholar
  33. XUE, T., KUH, E. S., AND YU, Q. 1996. A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies. In Proceedings of the IEEE MCM Conference, (Santa Cruz, CA, Feb.) 117-121. Google ScholarGoogle Scholar

Index Terms

  1. Optimal wiresizing for interconnects with multiple sources

                      Recommendations

                      Reviews

                      Andrew Donald Booth

                      Although it was realized in the 1940s that the lengths, capacitances, resistances, and inductance parameters of interconnections for high-speed computers are critical and, in fact, the original Princeton machine used three-dimensional layouts to optimize them, it is only recently that the same constraints have applied to such things as CPU chips for desktop computers. This paper formulates optimization functions for multiple source and sink, multiply connected networks. It also establishes techniques to achieve the optimizations. The authors claim that a suitable program has been produced. Numerous tables illustrate the expected gains, and there is an extensive bibliography.

                      Access critical reviews of Computing literature here

                      Become a reviewer for Computing Reviews.

                      Comments

                      Login options

                      Check if you have access through your login credentials or your institution to get full access on this article.

                      Sign in

                      Full Access

                      PDF Format

                      View or Download as a PDF file.

                      PDF

                      eReader

                      View online with eReader.

                      eReader