Ioana Burcea
ABSTRACT
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and performance. Ideally, BTBs would be sufficiently large to capture the entire working set of the application and sufficiently small for fast access and practical on-chip dedicated storage. Depending on the application, these requirements are at odds.
This work introduces a BTB design that accommodates large instruction footprints without dedicating expensive onchip resources. In the proposed Phantom-BTB (PBTB) design, a conventional BTB is augmented with a virtual table that collects branch target information as the application runs. The virtual table does not have fixed dedicated storage. Instead, it is transparently allocated, on demand, in the on-chip caches, at cache line granularity. The entries in the virtual table are proactively prefetched and installed in the dedicated conventional BTB, thus, increasing its perceived capacity. Experimental results with commercial workloads under full-system simulation demonstrate that PBTB improves IPC performance over a 1K-entry BTB by 6.9% on average and up to 12.7%, with a storage overhead of only 8%. Overall, the virtualized design performs within 1% of a conventional 4K-entry, single-cycle access BTB, while the dedicated storage is 3.6 times smaller.
- First the tick, now the tock: Next generation Intel microarchitecture (Nehalem). White Paper, Intel Co., 2008.Google Scholar
- Anastassia Ailamaki, David J. DeWitt, Mark D. Hill, and David A.Wood. DBMSs on a modern processor: Where does time go? In Proceedings of the 25th International Conference on Very Large Data Bases, 1999. Google ScholarDigital Library
- Alaa R. Alameldeen and David A. Wood. Variability in architectural simulations of multi-threaded workloads. In Proceedings of the 9th International Symposium on High-Performance Computer Architecture, 2003. Google ScholarDigital Library
- Murali Annavaram, Trung Diep, and John Shen. Branch behavior of a commercial OLTP workload on Intel IA32 processors. In Proceedings of the IEEE International Conference of Computer Design, 2002. Google ScholarDigital Library
- Luiz Andre Barroso, Kourosh Gharachorloo, and Edouard Bugnion. Memory system characterization of commercial workloads. In Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998. Google ScholarDigital Library
- Ioana Burcea and Andreas Moshovos. Virtualizing branch target buffers. Technical report, University of Toronto, 2008. www.eecg.toronto.edu/~ioana/papers/pbtb tech rep.pdf.Google Scholar
- Ioana Burcea, Stephen Somogyi, Andreas Moshovos, and Babak Falsafi. Predictor virtualization. In Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008. Google ScholarDigital Library
- Po-Yung Chang, Eric Hao, and Yale N. Patt. Target prediction for indirect jumps. In Proceedings of the 24th Annual International Symposium on Computer Architecture, 1997. Google ScholarDigital Library
- Karel Driesen and Urs Holzle. The cascaded predictor: economical and adaptive branch target prediction. In Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture, 1998. Google ScholarDigital Library
- Philip G. Emma, Allan M. Hartstein, Brian R. Prasky, Thomas R. Puzak, Moinuddin K. A. Qureshi, and Vijayalakshmi Srinivasan. Context lookahead storage structures. IBM, U.S. Patent 7337271 B2, 2008.Google Scholar
- Barry Fagin and Kathryn Russell. Partial resolution in branch target buffers. In Proceedings of the 28th Annual International Symposium on Microarchitecture, 1995. Google ScholarDigital Library
- Nikolaos Hardavellas, Stephen Somogyi, Thomas F. Wenisch, Roland E. Wunderlich, Shelley Chen, Jangwoo Kim, Babak Falsafi, James C. Hoe, and Andreas G. Nowatzyk. Simflex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture. SIGMETRICS Performance Evaluation Review, 31(4), 2004. Google ScholarDigital Library
- R. B. Hilgendorf, G. J. Heim, and W. Rosenstiel. Evaluation of branch-prediction methods on traces from commercial applications. IBM Journal of Research and Development, 43(4), 1999. Google ScholarDigital Library
- Daniel A. Jimenez. Reconsidering complex branch predictors. In Proceedings of the 9th International Symposium on High-Performance Computer Architecture, 2003. Google ScholarDigital Library
- Daniel A. Jimenez, Stephen W. Keckler, and Calvin Lin. The impact of delay on the design of branch predictors. In Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture, 2000. Google ScholarDigital Library
- Jose A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, and Yale N. Patt. Improving the performance of object-oriented languages with dynamic predication of indirect jumps. In Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008. Google ScholarDigital Library
- David R. Kaeli and Philip G. Emma. Branch history table prediction of moving target branches due to subroutine returns. In Proceedings of the 18th Annual International Symposium on Computer Architecture, 1991. Google ScholarDigital Library
- Kimberly Keeton, David A. Patterson, Yong Qiang He, Roger C. Raphael, and Walter E. Baker. Performance characterization of a Quad Pentium Pro SMP using OLTP workloads. In Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998. Google ScholarDigital Library
- Chetana N. Keltcher, Kevin J. McGrath, Ardsher Ahmed, and Pat Conway. The AMD Opteron processor for multiprocessor servers. IEEE Micro, 23(02), 2003. Google ScholarDigital Library
- Ryotaro Kobayashi, Yuji Yamada, Hideki Ando, and Toshio Shimada. A cost-effective branch target buffer with a two-level table organization. In Proceedings of the 2nd International Symposium of Low-Power and High-Speed Chips (COOL Chips II), 1999.Google Scholar
- Johnny K. F. Lee and Alan Jay Smith. Branch prediction strategies and branch target buffer design. Computer, 17(1), 1984. Google ScholarDigital Library
- Tao Li, Ravi Bhargava, and Lizy Kurian John. Adapting branch-target buffer to improve the target predictability of java code. ACM Transactions on Architecture and Code Optimization, 2(2), 2005. Google ScholarDigital Library
- Albert Meixner and Daniel J. Sorin. Unified microprocessor core storage. In Proceedings of the 4th International Conference on Computing Frontiers, 2007. Google ScholarDigital Library
- Ravi Nair. Dynamic path-based branch correlation. In Proceedings of the 28th Annual International Symposium on Microarchitecture, 1995. Google ScholarDigital Library
- Chris H. Perleberg and Alan Jay Smith. Branch target buffer design and optimization. IEEE Transactions on Computers, 42(4), 1993. Google ScholarDigital Library
- Parthasarathy Ranganathan, Sarita Adve, and Norman P. Jouppi. Reconfigurable caches and their application to media processing. In Proceedings of the 27th Annual International Symposium on Computer Architecture, 2000. Google ScholarDigital Library
- Andre Seznec, Stephen Felix, Venkata Krishnan, and Yiannakis Sazeides. Design tradeoffs for the alpha ev8 conditional branch predictor. In Proceedings of the 29th Annual International Symposium on Computer Architecture, 2002. Google ScholarDigital Library
- Ed H. Sussenguth. Instruction sequence control. IBM, U.S. Patent 3559183, 1971.Google Scholar
- Tse-Yu Yeh and Yale N. Patt. Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors. In Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993. Google ScholarDigital Library
- Tse-Yu Yeh and Yale N. Patt. Alternative implementations of two-level adaptive branch prediction. In Proceedings of the 19th Annual International Symposium on Computer Architecture, 1992. Google ScholarDigital Library
Index Terms
- Phantom-BTB: a virtualized branch target buffer design
Recommendations
Phantom-BTB: a virtualized branch target buffer design
ASPLOS 2009Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and performance. Ideally, BTBs would be sufficiently large to capture the entire ...
Phantom-BTB: a virtualized branch target buffer design
ASPLOS 2009Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and performance. Ideally, BTBs would be sufficiently large to capture the entire ...
Micro BTB: a high performance and storage efficient last-level branch target buffer for servers
CF '22: Proceedings of the 19th ACM International Conference on Computing FrontiersHigh-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still ...
Comments