Abstract
A high-performance p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated on a glass substrate. We have investigated the electrical characteristics of short-channel p-type ELA poly-Si TFTs under off-state bias stress. We have found that the threshold voltage of the short-channel TFT (L = 1.5 µm) significantly shifted in the positive direction under off-state bias stress (ΔVTH = 2.71 V), whereas the threshold voltage of long-channel TFT (L = 7 µm) barely moved in the positive direction (ΔVTH = 0.11 V). This positive shift of threshold voltage in the short-channel TFT may be attributed to electron trapping at an interface between the poly-Si film and the gate oxide layer. In addition, we have extracted the length of the drain extension from an equation of the pseudo-lightly doped drain (LDD) model to verify the existence of free hole charges induced near the drain junction. The transfer characteristics of the forward and reverse modes after the off-state bias stress indicate that the electron trapping at the gate insulator/channel interface occurred near the drain junction region. The leakage current of the ELA poly-Si TFT was also suppressed without reducing the on-current level under the off-state bias stress due to the creation of a pseudo-LDD region.