Full-Bit Functional, High-Density 8 Mbit One Transistor–One Capacitor Ferroelectric Random Access Memory Embedded within a Low-Power 130 nm Logic Process

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Published 24 April 2007 Copyright (c) 2007 The Japan Society of Applied Physics
, , Citation K. R. Udayakumar et al 2007 Jpn. J. Appl. Phys. 46 2180 DOI 10.1143/JJAP.46.2180

1347-4065/46/4S/2180

Abstract

We report the electrical properties of a full-bit functional 8 Mbit one transitor–one capacitor (1T–1C) embedded ferroelectric random access memory (eFRAM) fabricated within a low-leakage 130 nm 5 lm Cu interconnect complementary metal oxide semiconductor (CMOS) logic process. To increase manufacturability and reliability margins, we have introduced a single-bit substitution methodology that replaces bits at the low-end of the original distribution with redundant elements leading to an increased signal margin. Further, we have fabricated a digital signal processor (DSP) using the eFRAM process flow and have shown that the operating frequency is nearly the same relative to the CMOS baseline. With the development of logic-compatible eFRAM, we have created a technology platform that enables ultra-low-power devices.

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10.1143/JJAP.46.2180