A Novel Fabrication Method for Polycrystalline Silicon Thin-Film Transistors with a Self-Aligned Lightly Doped Drain Structure

We have developed a novel and simple fabrication method for poly-Si thin-film transistors (TFTs) with a self-aligned lightly doped drain (LDD) structure. The feature of this method is the use of lateral etching of an n⁺ Si gate electrode to make an LDD region. The lateral etching is realized by plasma etching with SF₆ gas. It is found that the etching length in the lateral direction, which is equal to the LDD length, is proportional to the overetching time. Hence, the LDD length is controlled precisely by the overetching time. By applying the fabrication method to make poly-Si TFTs, we have succeeded in decreasing the OFF current by more than one order of magnitude without decreasing the ON current, compared with a conventional poly-Si TFT. It is concluded that our method has a tolerance sufficient to fabricate the LDD structure with a high ON/OFF current ratio.