Phase Logic Based on π Josephson Junctions

The transition to Josephson digital circuits with the representation of information in the form of phase jumps of the superconducting order parameter on heterostructures promises a radical increase in the degree of integration while maintaining high speed and energy efficiency. However, it is not yet possible to manufacture reproducible bistable Josephson junctions, which are necessary for the functioning of the previously proposed basic units of the phase logic. To solve this problem, the concept of phase logic based on π junctions is proposed and analyzed within the resistive model of Josephson heterostructures. The potential energy of such junctions has a single minimum, with a difference in the order parameters of the electrodes equal to π. It is demonstrated that the use of π junctions allows one to implement the entire set of logic devices necessary for the operation of digital computing devices based on phase logic.

For the wide application of digital circuits based on fast single-quantum (FSQ) logic with the representation of information in the form of the presence/absence of a magnetic flux quantum Ф 0 in the superconducting circuit of a logic cell, it is critically important to reduce their characteristic dimensions. Existing estimates [19] for the maximum element density in circuits using geometric inductance for information storage and superconducting "strips" for connections provide about 10 7 Josephson junctions per square centimeter. Further reduction of the planar dimensions of cells and distances between them is problematic because of the almost exponential growth of mutual inductances and crosstalk. The problem of miniaturization is especially significant in Josephson circuits intended for operation at ultralow temperatures in hybrid quantum-classical computers, where it is necessary to reduce the critical current of heterostructures in order to avoid excessive heating of the cryogenic system.
A promising solution to this problem is the transition to the so-called phase logic, which is based on two basic principles: -Information is stored in the phase of the bistable Josephson element rather than in the presence/absence of a magnetic flux quantum in the basic cell.
-Circuit solutions are free of connecting inductances; i.e., electrical circuits contain only Josephson junctions.
A pair of logic states 0 and 1 can be obtained even using a single bistable Josephson junction [20][21][22][23][24]. In this case, the information-storage element of logic devices is reduced to this single junction. Its state is determined by which of the two energy minima corresponding to the phase jump of the order parameter (element phase) or it is currently in. The information propagation corresponds to the wave of the phase change in the superconducting order parameter rather than to the propagation of the fluxon.
The proposed approach was used to develop compact, energy-efficient circuits for the practical implementation of phase logic and memory [25,26]. It was demonstrated that the characteristic planar dimensions of digital devices can be an order of magnitude smaller than traditional FSQ implementations (the ϕ ϕ 0 = ϕ ϕ 1 =

CONDENSED MATTER
area on the chip for an 8-bit adder can be reduced from more than 200 to 22 μm 2 ) [25]. Unfortunately, to date, the manufacture of bistable Josephson junctions with specified and reproducible parameters is only at the development stage.
In this work, we demonstrate that workable digital phase logic circuits can be designed on the basis of combinations of 0 and π junctions (with a currentphase dependence shifted by π), which provide the basic unit bistability necessary for this logic to work. It should be noted that the technology for manufacturing 0 and π junctions is well developed at present [27][28][29][30][31].

GENERAL PRINCIPLES OF THE OPERATION
OF PHASE LOGIC CIRCUITS Figure 1 demonstrates the diagram of the basic unit of the phase logic on which elements with two stable physically distinguishable states are presented in the form of eight-pointed crosses, which correspond to phases of potential energy minima and ( and ). Note the absence of inductances in the basic unit, which are intended to store magnetic flux quanta. In the supply Josephson transmission lines, all connecting geometric inductances are also replaced by Josephson ones.
Information in this basic unit is stored in the phase of the element J m : its potential energy has two minima at and , respectively. The Josephson junctions J in and J out are the input and output ports of the circuit, respectively. The element J l connects the information-storage element J m to the output of the circuit J out . Its parameters primarily affect the state reading mechanism. The bistable element connects the input of the circuit to J m , acting as a phase converter at the input of the unit.
Depending on the parameters of the phase converter (which can be either one bistable junction or a serial connection of a pair of Josephson heterostructures [32]), the basic unit can perform all the modes necessary to implement the most common digital devices. Let us further consider the dynamic processes in the basic unit for the limiter mode, transmission line mode, and digital frequency divider mode.
In the limiter mode (top panel of Fig. 1), the incoming phase jump of the superconducting order parameter generates currents in the input cell, which lead to a phase change at the junction J in and the converter element by ~2π. However, the relation between the Josephson energies and the characteristic times of the processes for and J m is such that the phase converter switches between stable states before the information storage unit. The element J m and the output cell remain in this mode in their original equilibrium states. The phase difference jump at the output of the unit is not formed. Sequential switching of Josephson junctions (J in ) and bistable elements ( ) is demonstrated by arrows in the top panel of Fig. 1.
In the transmission line mode (middle panel of Fig. 1), the converter switches slowly, and the phase jump wave applied to the input creates a high current through it, changing the phases of the junction J in , as well as the central element J m and the output cell J out by ~2π. In this case, the input pulse carrying the phase change by 2π passes through the basic unit without changing its state. Sequential switching of Josephson junctions (J in , J out ) and bistable elements (J m ) is also demonstrated in the middle panel of Fig. 1

by arrows.
For intermediate values of the switching speed between stable states ( and ) of the converter , under the action of information coming to the input, the information-storage element J m has time to change its phase from to . As a result, the status of the basic unit as a whole changes from 0 to 1; i.e., a write operation occurs. In the bottom panel of Fig. 1, this is indicated by half of the standard arrow. Note that the amplitude of the current pulse arising in the output cell (J l − J out ) after one wave of phase jumps arriving at the input is not enough to switch the junction J out . However, after switching the basic element J m , the state of the output cell changed: the current began to circulate in it (what can be used to read information). When the circulating current is added to the current v v v pulse caused by the next phase change wave applied to the input, J out switches between its stable states (with phases 0 and 2π) and generates a phase change wave into the output line. In this case, the information-storage element J m returns from the state 1 to the state 0.
In the bottom panel of Fig. 1, this is indicated by the second half of the standard arrow. It can be concluded that the basic unit in this case operates as a digital frequency divider in half: every second pulse passes to the output of the circuit. It was shown [25] that on the basis of circuits with the described functionality, it is possible to implement logic elements, memory with destructive and nondestructive readout, RS and T flip-flops, half-adders, and more complex components of computing devices.

PHASE LOGIC CIRCUTS BASED ON π JUNCTIONS
In [21,[33][34][35][36], it was demonstrated how the coexistence of 0 and π junctions allows obtaining a bistable ϕ junction. The key idea of this work is that the required bistable elements of the phase logic unit can be created by combining relatively easy-to-make 0 and π Josephson junctions. Figure 2 demonstrates a version of the basic logic unit, in which the phase converter is made as a combination of 0 and π junctions (J 0C and J πC ). The π structure can also be used as the central element of the unit J m .
The total Josephson energy of the input cell, consisting of the junctions J in , J 0C , J πC , and J m , as a function of the phase difference at the junctions J in and J m , has two local minima (see Fig. 3). It can be seen that the phase in stable states is equal to π + 2πn at π junctions and to 2πn at 0 junctions, where n is an integer.
In this case, the input cell has an even number of π junctions, the total phase shift of the order parameter along the circuit is 2πn, and there is no circulating current. This excludes unwanted feedback on the other units and allows one to conveniently connect phase logic circuits to standard FSQ logic elements. Note that a bistable input cell could be obtained without the use of π junctions, by introducing instead of them a large number of series-connected 0 structures that provide the phase shift of the order parameter. The output cell has an odd number of π junctions, so the difference between the phase J m and the phase of 0 junctions creates a circulating current in it, which can flow in two directions, which allows one to read the state of the unit. This forces a drop in the phase of the order parameter π on the element J l . It turns out that, for the stable operation of the circuit, it is optimal to implement such an element in the form of a stack consisting of three junctions J l1-3 connected in series.
To demonstrate the operability of all the key information processing modes listed above, the dynamic processes in the basic unit demonstrated in Fig. 2 are considered. When modeling the control processes and reading the state of the basic unit, the transmission lines consisting only of Josephson junctions will be considered [25]. The system of differential equations, taking into account the balance of currents for each node, was written within the generalized resistive model and was solved using the fourth and fifth order Runge-Kutta methods, as well as the Gauss method  where is the total current flowing into the junction, i Cj is the critical current, and is the damping factor. All currents are represented in units of the critical current of the input junction; the dot denotes the differentiation with respect to the time τ measured in units of the characteristic time of the input junction τ C . Thus, in the limiter mode (Fig. 4а), when the critical current of the junction J πC is slightly less than that of the junction J 0C , the π structure is the "weak point" in the input cell, at which a phase jump of ~2π occurs. In this case, the phases of the junctions J m and J out hardly change. In the transmission line mode (Fig. 4b), each phase change wave at the input changes the phase of the junctions J m and J out by 2π and then propagates to the output transmission line. The pulses pass through the basic unit without changing its state: at the end of the calculation given for illustration, π + 8π. In the frequency-halving mode, each pulse at the input changes the phase of the junction J m by ~π (i.e., in this case, and ), but only every second pulse changes the phase of the junction J out by 2π.
It is possible to select the operating mode of the unit (limiter, transmission line, digital frequency divider) by selecting the critical currents i 0C and i πC of the 0 and π junctions, respectively (Fig. 5). It is clearly seen that the limiter mode is implemented when switching between neighboring stable states in the phase converter in the input cell occurs earlier than in J m . It can be seen from the equation of motion (1) that the rate of phase change at the junction is determined by the parameter . However, if the slow junction has a relatively low critical current, it may start switching earlier.  Fig. 3; and . In practice, 0 Josephson junctions are usually superconductor-insulator-superconductor (SIS) tunnel heterostructures of the "sandwich" type. Compatible with FSQ circuits and quantum registers, π junctions are created in the form of superconductor-ferromagnet-superconductor (SFS) heterostructures with a sufficiently large critical current and a low resistance in the normal state [27,28,37,38]. As a consequence, such π Josephson junctions have a low characteristic voltage and a low characteristic frequency [39][40][41][42]. Taking into account a low speed of π junctions in comparison with 0 junctions, we found that the operation of the cell is slowed. Figure 6 demonstrates that the duration of one working cycle of the circuit increases by a factor of about 1.5. In addition, the frequency-halving region on the plane of the junction parameters, which is a part of the phase converter, is narrowed (Fig. 5). This problem can be solved by switching to stacks, starting from the concept of a superconductor-insulator-superconductor-ferromagnet-superconductor (SIsFS) heterostructure.
For such composite junctions, the characteristic voltage and frequency are of the same order as for tunnel Josephson junctions used in FSQ logic circuits [39][40][41][42].
The use of nanoscale (with an area of 18000-30000 nm 2 ) Josephson junctions with a weak bond region made of a normal metal, constructed in the form of a bridge of variable thickness, is also promising [43,44]. Since the functional geometric inductance is replaced by the Josephson one in the proposed basic unit, such a solution will provide a particularly noticeable gain in the compactness of the developed digital devices. Using this approach, π junctions can be obtained by using additional magnetic insulating layers in the weak-coupling region.

CONCLUSIONS
To summarize, a circuit has been proposed to implement the entire functionality of phase logic circuits without using bistable Josephson junctions [45], which are difficult to manufacture. At the same time, one of the key advantages of the approach under consideration, i.e., small planar dimensions of the circuits and, as a result, the possibility of achieving a high degree of integration for Josephson digital devices, can be retained. To reduce the planar dimensions of the proposed block, Josephson junctions (e.g., junctions J l1-3 in the output cell) can be made in the form of a compact stack [46].
The planar size of the proposed basic unit can be estimated as the sum of the areas of all Josephson junctions of the circuit and the sum of the areas of connections between them. Under the assumption that the areas of all junctions are equal to S, and the same area is occupied by the connections, then the area of the basic unit is 14S. In the case of the MIT LL technology for superconductor-insulator-superconductor tunnel structures, μm 2 [47], and the area of the basic unit will be approximately 5.6 μm 2 . In the case of a nanoscale Josephson junction with a weak bond region made of a normal metal, constructed in the form of a bridge of variable thickness [43], the required area is μm 2 , and the area of the basic unit is 0.252 μm 2 . The indicated marks make the prospects for the practical implementation of the Josephson phase logic circuit based on π junctions very relevant.