Abstract
Proposed was an extension to the class of multistage Clos networks based on the interstage connection circuit described by the balanced incomplete block designs considered in the combinatorics.
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References
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Nikolaev, A.B. and Podlazov, V.S., Fault-Tolerant Expansion of System Area Networks in Multiprocessor Computer Systems, Autom. Remote Control, 2008, no. 1, pp. 150–157.
Nikolaev, A. and Podlazov, V., The Fault-tolerant Extension of System Area Networks of Multiprocessor System, Proc. 17 IFAC World Cong., Seoul, 2008, pp. 10622–10667.
Karavai, M.F., Parkhomenko, P.P., and Podlazov, V.S., Combinatorial Methods for Constructing Bipartite Uniform Minimal Quasicomplete Graphs (Symmetrical Block Designs), Autom. Remote Control, 2009, no. 2, pp. 312–327.
Karavai, M.F., Parkhomenko, P.P., and Podlazov, V.S., Simple Methods to Construct Quasicompletely Connected Graphs (Symmetrical Block Diagrams), Proc. IV Int. Conf. “Parallel Computations and Problems of Control” PACO’2008, Moscow: Inst. Probl. Upravlen., pp. 232–249.
Guide to Myrinet-2000 Switches and Switch Networks, Manuscript at http://www.myti.com/myrinet/m3switch/guide.
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Original Russian Text © V.S. Podlazov, V.V. Sokolov, 2009, published in Avtomatika i Telemekhanika, 2009, No. 10, pp. 158–171.