Electrical linewidth metrology for sub-65-nm applications

Greet Storms; Shaunee Cheng; Ivan Pollentier

doi:10.1117/12.537346

24 May 2004 Electrical linewidth metrology for sub-65-nm applications

Greet Storms, Shaunee Cheng, Ivan Pollentier

Proceedings Volume 5375, Metrology, Inspection, and Process Control for Microlithography XVIII; (2004) https://doi.org/10.1117/12.537346
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

For the 100nm technology node, the electrical measurement technique continues to play an important role as a metrology tool for generating large volumes of unbiased and statistically significant CD data. However, the ECD offset of approximately 35 to 40nm between the SEM CD after etch and the electrically measured CD obtained with the current standard ELM process, is a potential limitation for applying ELM to feature sizes below 65nm. Is this ECD offset process related or have we reached the limitation of the metrology technique fundamental to ELM? These are questions we attempt to answer in this paper. This paper attempts to answer these questions by looking at the fundamentals of the metrology technique and the influence of substrate material on the ECD offset. A calibration of the offset is performed by benchmarking ECD against different CD-SEM measurement algorithms. We re-examine the basic assumption that is fundamental to the electrical measurement technique and examine if this still holds true when the CD has become smaller although the substrate thickness has remained constant? In conclusion we report the parameters influencing the ECD to physical measurement bias and the limitations of this measurement technique.

Citation Download Citation

Greet Storms, Shaunee Cheng, and Ivan Pollentier "Electrical linewidth metrology for sub-65-nm applications", Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); https://doi.org/10.1117/12.537346

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