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The assembly of superconducting millimeter and submillimeter-wave circuits often requires RF ground connections. These are usually made by soldering, wire bonding, conductive adhesive or conductive wire gaskets. The difficulty of assembly increases with frequency as chip dimensions and tolerances shrink. The assembly issues, and also the throughput requirements of large radio astronomy projects such as ALMA (Atacama Large Millimeter Array), suggest the need of a beam lead technology for these circuits. Beam lead processes are already established for silicon and gallium arsenide wafers. However, niobium circuits on quartz substrates present unique difficulties. SIS junctions introduce additional thermal and chemical constraints to process development. For quartz, wet etches are isotropic and dry etches with high etch rates require large ion energies. Therefore, it is difficult to develop a conventional process in which gold pads on the substrate surface are formed into beam leads by a backside etch. Instead we have developed a topside process in which, after the mixer circuits are completed, dicing cuts are made at the finished chip dimensions but only partly through the wafer. The dicing cuts are then filled with a sacrificial material in a non-CMP process, and planarized. Gold plated pads are then defined, overhanging the planarized cuts. The sacrificial material is then removed from these cuts, leaving the gold beam leads. The wafer is then backside lapped into the cuts to the desired thickness, separating the individual chips. We discuss the new planarization scheme developed for this beam lead process and compare a variety of sacrificial materials.
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