Presentation + Paper
20 March 2019 Scanner and etch co-optimized corrections for better overlay and CD control
Author Affiliations +
Abstract
With shrinking design rules, the overall patterning requirements are getting aggressively tighter and tighter, driving requirements for on-product overlay performance below 2.5nm and CD uniformity requirements below 0.8nm. Achieving such performance levels will not only need performance optimization of individual tools but a holistic optimization of all process steps. This paper reports on the first step towards holistic optimization – co-optimized performance control of scanner and etch tools. In this paper we evaluate the use of scanner and etcher control parameters for improvement of after final etch overlay and CD performance. The co-optimization of lithography and etch identifies origins of the variabilities and assigns corrections to corresponding tools, handles litho-etch interactions and maximizes the correction capability by utilizing control interfaces of both scanner and etch tools in a single control loop. The product aims to improve total variability measured after etch as well as fingerprint matching between tools. For CD control we co-optimize the dose corrections on the lithography tool with the temperature corrections on the etcher. This control solution aims to correct CD variabilities originating at deposition, lithography and etcher. For overlay we co-optimize the overlay inter and intra-field grid interfaces on the scanner with the wafer edge ring height compensation on the etcher. The evaluation of both CD and overlay control solutions is performed for the 2xnm DRAM node of SK hynix DRAM group. YieldStar in-device metrology after core etch was used for CD control. On wafer verification showed an improvement of 23% of the total CD variation. In-device metrology after final etch was user for overlay control. Evaluation showed 35% improvement in total overlay variability due to scanner-etch co-optimization.
Conference Presentation
© (2019) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ik-Hyun Jeong , Seung-Woo Koo, Hyun-Sok Kim, Jae-Wuk Ju, Young-Sik Kim, Yong-Tae Cho, Heung-Joo Kim, Katja Viatkina, Tom van Hemert, Ruud de Wit, David Deckers, Owen Chen, Nang-Lyeom Oh, Marcus Musselman, Marcus Carbery, Ssuwei Chen, Lucian Schmidt, Heidi Kwon, and Jae Gyoo Lee "Scanner and etch co-optimized corrections for better overlay and CD control", Proc. SPIE 10963, Advanced Etch Technology for Nanopatterning VIII, 1096308 (20 March 2019); https://doi.org/10.1117/12.2516578
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KEYWORDS
Etching

Overlay metrology

Scanners

Semiconducting wafers

Metrology

Critical dimension metrology

Lithography

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