Solving clock distribution problems in FDDI concentrators

Gabriel M. Li

doi:10.1117/12.24613

1 February 1991 Solving clock distribution problems in FDDI concentrators

Gabriel M. Li

Proceedings Volume 1364, FDDI, Campus-Wide, and Metropolitan Area Networks; (1991) https://doi.org/10.1117/12.24613
Event: SPIE Microelectronic Interconnect and Integrated Processing Symposium, 1990, San Jose, United States

Abstract

This paper addresses the advantages of using a concentrator for inserting or removing a station onto or from the Fiber Distributed Data Interface (FDDI) ring. It gives an overview of the architecture of a FDDI concentrator. It highlights major data and clock distribution problems in a backplane bus. The main focus is a design example of a small and large concentrator using the National Semiconductor FDDI chipset. Different timing contraints such as setup and hold data and clock flight time and flight time cancellation are discussed in detail.

Citation Download Citation

Gabriel M. Li "Solving clock distribution problems in FDDI concentrators", Proc. SPIE 1364, FDDI, Campus-Wide, and Metropolitan Area Networks, (1 February 1991); https://doi.org/10.1117/12.24613

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