43 years overlay metrology in microlithography: How did we get here?Holistic Lithography: where we are today The future of Holistic lithography: where we are going Summary
43 years overlay: 3 orders of magnitude down1  43 years overlay: 3 orders of magnitude down1 1973: Introducing the first 1:1 wafer stepper, ~0,5 εm overlay  43 years overlay: 3 orders of magnitude down1  43 years overlay: 3 orders of magnitude down1  43 years overlay: 3 orders of magnitude down, Steppers1 1979: 4-parameter reticle to wafer diffraction-based alignment  43 years overlay: 3 orders of magnitude down, Steppers1 1986: 8-parameter alignment  43 years overlay: 3 orders of magnitude down, Steppers1 1987-97: Increased correctables on step and scan  Buckley, C Karatzas, “Step and scan, a system overvieuw of a new lithography tool,”, Proc. SPIE vol 1088, Optical laser lithography II, march 1989, M.van den Brink, H,Jasper, S.Slonaker, P.van Wijnhoven, Frans Klaassen, “Step and Scan and Step and Repeat, a technology comparison” Proc. SPIE vol. 2726, Symposium on Micro lithography IX, march 1996 43 years overlay: 3 orders of magnitude down, Steppers1 2000: Multi-color alignment increased process robustness  43 years overlay: 3 orders of magnitude down, Steppers1 2001: Increased metrology time at higher productivity using dual stage  43 years overlay: 3 orders of magnitude down, Steppers1 2007: Small process-compatible alignment markers by self-referencing  M. Miyasaki, H.Saito, T.Tamura, T.Uchiyama, P.Hinnen, H.W.Lee, M.van Kemenade, M.Shahrjerdy, R.van Leeuwen, “The application of SMASH alignment system for 65-55 nm logic devices. Proc. SPIE vol. 6518, Metrology, inspection and process control for microlithography XXI February 2007, A den Boef, “Optical wafer metrology sensors for process-robust CD and overlay control in semiconductor device manufacturing”,Surf. Topogr.: Metrol. Prop. 4 (2016) 023001 43 years overlay: 3 orders of magnitude down, corrections1 User-definable correction capability increased ~4 orders of magnitude  43 years overlay: 3 orders of magnitude down, corrections 1979: Manual stepper setup using verniers on reduction steppers  William. C. Schneider, “Testing The Mann Type 4800DSWTM Wafer Stepper” , Proc. SPIE vol. 0174, Developments in Semiconductor Microlithography IV, April, 1979 43 years overlay: 3 orders of magnitude down, corrections1 1982: 8-parameter stepper overlay setup model  43 years overlay: 3 orders of magnitude down, corrections 1988: 25-parameter automatic alignment setup  M. A. van den Brink ; C. G. de Mol ; R. A. George, “Matching Performance For Multiple Wafer Steppers Using An Advanced Metrology Procedure”, Proc. SPIE vol. 0921, Integrated Circuit Metrology, Inspection, and Process Control II, march, 1988 43 years overlay: 3 orders of magnitude down, corrections 1993: i-line to DUV automated 99-parameter 8-machine matching setup  Martin A. van den Brink; Chris G. M. de Mol; Judon M. D. Stoeldraijer ,“Matching of multiplewafer steppers for 0.35-μm lithography using advanced optimization schemes”, Proc. SPIE vol.1926, Integrated Circuit Metrology, Inspection, and Process Control VII, February, 1993 43 years overlay: 3 orders of magnitude down, corrections1 2007: 20-parameter higher-order user-definable corrections per field  43 years overlay: 3 orders of magnitude down, feedback1 1993: Stepper external feedback control  43 years overlay: 3 orders of magnitude down, feedback 2000: Stepper advanced process control  43 years overlay: 3 orders of magnitude down, feedback1 2008: Litho feedforward and feedback control  43 years overlay: 3 orders of magnitude down, feedback1 2012: Small target design allowing on-product targets  43 years overlay: 3 orders of magnitude down1  43 years overlay metrology in microlithography: How did we get here?
Holistic Lithography: where we are todayThe future of Holistic lithography: where we are going Summary
ASML holistic lithography: 6 competences  1) Advanced Lithography: significantly improved on critical parameters both for immersion as well EUV  2) Metrology: boosts performance and productivity Increase metrology accuracy, cut cost of metrology by a factor of 4  3) Computational Lithography: Robust modeling capability Negative Tone Development (NTD) resist with physical modeling accuracy improved 59%  4) Process Window Enhancement: EUV optimization over an increasingly large parameter space improves window 27%  5) Metrology: >30% improved wafer edge overlay on Memory process stack using integrated and diffraction-based overlay metrology, fingerprint capturing and sampling optimization  6) Process Window Detection: Engineering efficiency improvement by computational assisted alignment marker, recipe and sampling scheme optimization  43 years overlay metrology in microlithography: How did we get here? Holistic Lithography: where we are today
The future of Holistic lithography: where we are goingSummary
Challenges by balancing sampling and correction density Improved noise suppression by determining fingerprint capture  Fingerprint capturing will improve correction noise  Fingerprint modeling can decrease # parameters >10x resulting in better capturing the errors and reducing noise  Reducing overlay by 25% and improving edge yield Using an optimized sampling scheme  43 years overlay metrology in microlithography, how did we get here Holistic Lithography; where are we today
The future of Holistic lithography, where are we goingThe future of Holistic lithography: where we are goingSummary
Pattern fidelity is impacted by multi-patterning and variability Edge placement error affected by overlay and CD variations  Data courtesy IMEC 10-nm logic design (M1) CD variation after etch effectively controlled with scanner Self-aligned double patterning fidelity optimized by balancing spacers S1 and S2  CD fidelity improved by 2x using higher-order corrections  J. Lee et. al, “Spacer multi-patterning control strategy with optical CD metrology on device structures” SPIE conference 9778-80, February 2016 Challenge in pattern fidelity and control  Patterning fidelity litho control impact, the next holistic step Using computational prediction allowing per wafer patterning control  Source: Imec 10 nm SuperNova M1A Extension of control loops to patterning and fidelity  Pattern fidelity improvement through scanner corrections  43 years overlay metrology in microlithography: How did we get here? Holistic Lithography: where we are today The future of Holistic lithography: where we are going Summary
Future trends in holistic lithography – overlayIn general for overlay and pattern fidelity:
What we observe for overlay:
Overlay contribution from wafer deformation and marker fidelity vs stepper accuracy is increasing in the total overlay budget Wafer deformation and marker fidelity variation from wafer to wafer starts contributing in the overlay
As a consequence for overlay
There needs to be a consistent trend down in cost per measurement for metrology to allow higher sampling density Sampling schemes need to be optimized capturing the relevant parameter instability and allow averaging to reduce noise Above will allow scanner correction capability moving from feedback per batch on global targets to feedback per wafer on intra-die product structures
Future trends in holistic lithography – pattern fidelity
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