Experimental and Numerical Analysis of Off-State Bias Induced Instabilities in Vertical GaN-on-Si Trench MOSFETs

We analyzed the threshold-voltage dynamic instabilities induced by <sc>off</sc>-state stress in pseudo-vertical GaN-on-Si Trench <sc>mosfet</sc>s (TMOS). Extensive measurements revealed that <sc>off</sc>-state stress experiments induce a progressive increase of threshold voltage (<italic>V<sub>T</sub></italic>), that is fully recoverable only after high-temperature cycles, so that it can appear as permanent degradation at room temperature. <italic>V<sub>T</sub></italic> increase is found to be strongly affected by drain bias and negligibly influenced by gate bias (below threshold). Activation energy (<italic>E<sub>A</sub></italic>) extracted from high-temperature <italic>V<sub>T</sub></italic> recovery experiments was determined to be ≈1 eV. We further characterized pseudo-vertical <italic>p–n</italic> junction diodes fabricated onto the same wafer as the TMOS's by means of capacitance isothermal spectroscopy. This experiment revealed depletion capacitance (<italic>C</italic><sub>DEP</sub>) instabilities with the same <italic>E<sub>A</sub></italic> as that characterizing the <italic>V<sub>T</sub></italic> instability, leading to the conclusion that trap states present in the epitaxy are the cause of both observations. Numerical device simulations guided the physical interpretation of the observed phenomena, i.e., donor traps at 1 eV from the conduction band and localized in the <italic>p-</italic>layer lead to both <italic>V<sub>T</sub></italic> and <italic>C</italic><sub>DEP</sub> instabilities in the TMOS and in the <italic>p–n</italic> diode, respectively, by dynamically modulating the effective <italic>p</italic>-type doping density in the former and the effective depletion layer width in the latter.


I. INTRODUCTION
V ERTICAL GaN-on-Si devices are a potential cost- effective alternative compared to Si and SiC counterparts for high power switching applications [1], [2].While GaNon-Si pseudo-vertical diodes with breakdown voltage (V BR ) in the 800-900 V range [3], [4] and with avalanche capability [5] have already been proven in research labs, the challenge of delivering high performance and reliability on large-scale wafers (>200 mm) is yet to be overcome [6].Moreover, vertical transistors, such as trench MOSFETs (TMOS's) present further hurdles compared to diodes related to the gate stack such as mobility degradation, threshold voltage (V T ) instability and oxide breakdown [7], [8], [9], [10].These issues need to be characterized under bias conditions relevant for power switching applications, so that their significance for practical applications can be readily assessed.
In this article, we extensively characterize V T instabilities during OFF-state stress experiments.Instability refers to any recoverable parametric change in device characteristics during operation as a consequence of dynamic effects associated with traps present in the device structure.The stress experiments carried out in this article allow quantifying the cumulative effect on device V T of OFF-state operating conditions applied, for instance, in switching converters.Interestingly, the observed V T increase was found to be positively correlated with increasing drain bias while not being significantly influenced by gate bias, suggesting that the mechanism is related with device epitaxy rather than gate stack.V T recovery was assessed at zero bias at different temperatures and a ≈1-eV activation energy (E A ) was extracted from the Arrhenius plot of the process.Further characterization was carried out on pseudo-vertical p-n junction diodes -with the same epitaxy as that of the TMOS's-by means of capacitance isothermal spectroscopy (C-ITS).These experiments revealed an increase of the depletion capacitance (C DEP ) under reverse bias conditions, accelerated by temperature with the same E A as that extracted from the V T recovery.This correlation points to trapping effects occurring in the device epitaxy as the mechanism behind both observations.
Particularly, V T increase during OFF-state stress experiments is attributed to the charging of donor traps in the p-body region by electrons leaking from source to drain under subthreshold conditions.The observations drawn from experiments were supported by calibrated numerical simulations that reproduced well both V T instability and C DEP increase when including deep donor traps in the p-type body region with 1-eV ionization energy (with respect to GaN conduction band).Finally, we discuss the possible origin of these epitaxy trap states and quantify their impact on the efficiency of a 36-12 V buck converter.
The rest of the article is organized as follows.Section II gives an overview of reliability aspects of GaN devices, particularly focusing on the comparison between lateral and vertical normally-off transistors.In Section III the devices characterized in this article are described.Section IV presents the experimental results.Section V discusses the model proposed to interpret the experiments and the results of the numerical simulations that confirm the interpretation.Finally, Section VI concludes this article.
The promises of the TMOS are: achieving high breakdown voltages (>1 kV) without increasing chip area, high V T values thanks to the inversion-mode operation, lower impact of trapping issues on R ON compared to lateral GaN devices.The latter point is true provided that the electric field in the OFF-state peaks in the drift region, away from the device surface and gate stack [2].Nevertheless, owing also to their lower maturity, vertical GaN devices are expected to suffer from charge-trapping related issues.These issues critically affect both conduction and switching losses because of the degradation of key electrical parameters (i.e., V T [7], R ON [15], as well as device capacitances [16]).
In general, trapping mechanisms can be classified depending on: the specific trap parameters determining their dynamics; the location of the traps within the complex device structure; the type of carriers being captured/emitted; and the charging/discharging path of the trap [2].
In practical terms, these aspects need to be considered either for technology optimization or for determining the proper device for the desired application.
Owing to their different topology, GaN lateral and vertical devices are generally affected by different trapping mechanisms, which in turn determine the drift of V T , and/or R ON .Table I summarizes the most relevant trapping mechanism in both lateral p-GaN HEMT's (i.e., the most common option in commercial applications) and vertical GaN TMOS's (under investigation in this article).
V T instability (ΔV T ) is determined by dynamic charge trapping occurring under the gate terminal in lateral devices (p-GaN, AlGaN barrier, GaN buffer) or in either the p-type body region or in the gate insulator in TMOS devices.This occurs because trapped charge affects the capability of the gate terminal to populate the channel-either formed thanks to the two-dimensional electron gas in HEMT's or to the inversion channel in TMOS's.
Dynamic R ON (ΔR ON ) is determined by trapping occurring in the gate-to-drain access region or drift region in lateral and vertical devices, respectively.The two regions in fact are the largest ones in the structure and as such dominate R ON .Both dynamic R ON increase and decrease can be observed depending on the operating conditions [20], [21], [22], [23].In TMOS's, dynamic R ON can adversely be affected by traps located along the trench sidewalls [15].

III. DEVICE DESCRIPTION
Devices under test consist of pseudo-vertical GaN TMOS's on a silicon substrate.The epitaxial stack, obtained by metalorganic chemical vapor deposition consists of a strain relief buffer layer, an n + drain layer (1 μm), an n − drift layer (1 μm), a p + body channel layer (500 nm), and a n + -GaN source layer (300 nm).The gate trench was formed with a Cl-based inductive coupled plasma reactive ion etching followed by a Tetramethylammonium hydroxide (TMAH) wet etching to achieve a vertical sidewall free of the plasma damage.Then, 70 nm silicon di-oxide gate dielectric was deposited by low-pressure chemical vapor deposition at a temperature of 880 °C, followed by a post-deposition annealing at 900 °C, to improve the mobility in the channel [24].The gate electrode was made out of polysilicon.
Drain contacts to the n+ layer were made from the frontside, laterally displaced with respect to the TMOS mesa structure, creating a pseudo-vertical device.
The structure is a simplified vesion of the classical TMOS that can nominally operate at low voltages, because of the relatively thin drift layer and the lack of thick bottom dielectric [25], [26], [27], or the p-type shielding [28] usually implemented in other technologies such as Si and SiC to optimize the breakdown voltage.The structure of the TMOS's under study is schematically reported in Fig. 2(a).As far as V T instability is concerned, performing the analysis on pseudo-or fully-vertical TMOS's does not affect the conclusions of this article, as the device region responsible for the parametric instability is not the drift region but the p-type body region which is the same in both structures.

IV. DEGRADATION CHARACTERIZATION
We characterized V T instability after OFF-state stress conditions at different bias and temperatures.We also characterized the deep levels in the semiconductor layers of a p-n diode (fabricated on the same wafer as that of the TMOS's) by means of capacitance C-ITS under reverse bias conditions.The latter experiments allowed gaining deeper insights into the mechanism underlying V T instability.
V T instability characterization was performed under moderate OFF-state stress conditions (i.e., V DS,STR = 0-40 V and ΔV DS = 10 V) [29].Fast V T transient were acquired as follows: device was stressed at a constant bias (V DS,STR ) which was periodically interrupted to sample V T by acquiring I D -V GS with a fast 10-μs gate voltage ramp, while keeping the drain bias at 5 V.
V T was defined as the necessary V GS to have I D = 1 mA.Fig. 3 shows a sketch of the voltage waveforms applied on the gate and drain terminals during these experiments.The same setup was also used to assess recovery, for which V DS,REC = 0 V. Stress and recovery maximum duration was 100 s.All these experiments were carried out at room temperature.To avoid any trapped charge accumulation, devices were exposed to 365 nm (3.4 eV) ultraviolet illumination for a few minutes between each stress measurement.
The I D -V GS acquired during stress with V DS,STR = 30 V are reported in Fig. 4(a), from which it can be observed how the stressed devices are subject to a V T increase, with negligible changes in terms of subthreshold slope and saturation current.The noisy off-state current for V GS < 2.5 V is limited by the inaccuracy of the autozero procedure applied to compensate the current probe offset.Fig. 4(b) shows instead I D -V GS acquired during recovery after 100-s stress at V DS,STR = 30 V, showing negligible ΔV T during the duration of the experiment.The features of V T instability can be further assessed with the aid Fig. 4(c) and (d), showing ΔV T (calculated with respect to the pre-stress value) during stress and recovery, respectively, acquired after different V DS,STR .
ΔV T during stress increases in magnitude (up to saturation) as well as accelerates with increasing V DS,STR , whereas ΔV T during recovery remains flat regardless of V DS,STR.These results are different from those obtained with gate-stress experiments [29], in which V T did not show saturation during 1000-s stress and partially recovered in 1000 s.V T instability during gate-stress experiments were attributed to traps located in the gate oxide near the semiconductor/insulator interface [7], [29].The different features of V T instability during OFF-state stress compared to gate stress lead to conclude that it is likely influenced by other mechanisms than oxide traps.
To identify the driving force of the mechanism underlying V T instability, we performed another set of transient characterization also by applying different V GS,STR < 0 V.This effectively increases V DG during OFF-state stress.The results of this characterization, along with the different combinations of (V DS,STR , V GS,STR ) are reported in Fig. 5. From Fig. 5 one can observe how V T increase is strongly affected by drain bias while it is negligibly influenced by gate bias.To understand why this is the case, we acquired drain and gate leakage currents during constant OFF-state stress experiments.These were carried out starting with V DS = 0 V with V GS = 0 V (i.e., below V T ) for 120 s.After the 120-s period elapsed, V DS was increased by 5 V and kept constant for another 120 s.
The process was repeated in a bias range for which catastrophic failure did not occur, i.e., up to V DS = 60 V.The results of this characterization are reported in Fig. 6, which shows that the drain leakage starts to increase at V DS = 15 V, and keeps increasing progressively up to V DS = 60 V. Instead, during the whole bias range gate leakage current stayed approximately  From all the experimental findings hitherto reported, one then concludes that V T instability is influenced by electron trapping occurring within deep levels located in the epitaxial structure (rather than in the gate oxide), that get filled by the source-drain leakage current.
The dynamic properties of the traps responsible for V T instability were determined by extracting V T transients at different temperatures.Stress at V DS,STR = 30 V was applied for 100 s, and then V T evolution was monitored at V DS = 0 V for 1000 s.The results reported in Fig. 7 show that to induce a significant V T decrease, high temperature (>150 °C) is required.Furthermore, by fitting V T decrease with a stretched exponential function following the procedure described in [30], the Arrhenius plot Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.  of the process can be built, see inset in Fig. 7.The extracted activation energy (E A ) is ≈ 0.97 eV.
Finally, to confirm that the traps responsible for the V T instability are related to the epitaxial structure, we performed an analysis of the deep levels on p-n diodes [on the same wafer as the TMOS's, see Fig. 2(b)] by means of capacitance C-ITS [31].In these structures the absence of the n-type source layer, and thus of the leakage current observed instead in TMOS's, allows us to single out the effect of electron emission from traps.
The experimental procedure consisted of two phases.First, the diode was biased at a filling voltage V F = 0 V for 100 s, such that any deep levels present in the junction are in a steady-state occupation condition.Then, the diode was reversely biased at V R = -30 V (i.e., the same used to monitor V T transients) for up to 1000 s and the depletion capacitance (C DEP ) transient was acquired.In this phase, trapped carriers emitted from traps can be assessed by looking at the variation of C DEP .Different temperatures were employed to accelerate carrier emission and to obtain an Arrhenius plot as previously.Results are shown in Fig. 8.The data were fitted with stretched exponential curves in the range attributed to carrier emission; the fitting curves are shown in Fig. 8 as dashed lines.The fitting curves were used to extract the time constants (τ 's) to build the Arrhenius plot of the process.The activation energy of the process, obtained from the Arrhenius plot shown in the inset of Fig. 8 is ≈1 eV, in very close agreement with that obtained from the V T transients of Fig. 7.This agreement confirms the hypothesis of traps being located in the epitaxy of the device to be the cause for V T instability in TMOS's and C DEP increase in p-n diodes.
V. NUMERICAL SIMULATIONS Two-dimensional numerical device simulations were performed with the device simulator included in the Synopsys technology CAD suite [32].Simulations were devoted to further elucidate the physical mechanism behind both V T instability and C DEP increase in TMOS's and p-n diodes, respectively.Simulated device cross sections resemble those of the actual devices, see Fig. 2. The simulation setup for the TMOS is based on the one employed in our previous work [7] where we investigated the role of interface and oxide traps on the subthreshold slope and the I-V hysteresis, respectively, in similar devices to the ones considered in this article.Drift-diffusion formalism was employed to simulate charge transport.Incomplete ionization of magnesium (Mg) acceptors was taken into account in the p-doped body region.The Mg ionization energy was set to 0.2 eV from the GaN valence band edge.The trap-occupation dynamics was accounted through the Shockley-Read-Hall (SRH) trap-balance equation without any quasi-static approximation.We included deep donor traps in the p-doped body region with 1-eV ionization energy with respect to GaN conduction band edge.The particular choice for location within the epitaxy stems from the modeling of C DEP increase in the p-n diodes, explained in the following.
The ionization energy of these traps is set equal to the E A extracted from the experiments.Concentration of traps was set to N D 17 cm -3 .The same bias conditions and timing that were used during characterization (see Section IV-C) were replicated in the simulation setup.Fig. 9 shows the relative C DEP increase when considering donor traps either in the p-type body, in the n-type drift, and in both regions.As it can be observed, in all cases C DEP increases over emission time.This happens as a result of the reduction of the depletion layer width on the n-side by the emitted electrons.C DEP increase is accelerated by temperature, as expected from SRH theory.The E A extracted from the Arrhenius plot (not shown) in all cases was 1 eV as expected.However, Fig. 9(a) is the only case for which ΔC DEP quantitatively agrees with experimental observations.For the sake of comparison, the inset in Fig. 9(a) reports ΔC DEP obtained from the fitting curves of experimental data.We assume from now on that traps are located only in the p-type body region.
Then, we simulated the V T recovery transients in TMOS's corresponding to experiments in Fig. 6, starting from an initial condition with filled donor traps.This condition corresponds to the end of the stress period, during which donor traps are filled by source-drain leakage electrons.In this simulation, N D = 3 × 10 17 cm -3 to get a quantitative agreement with experiments in terms of magnitude of ΔV T .Fig. 10 shows  the simulation results, from which one can observe how ΔV T is accelerated by temperature with E A = 1 eV (see inset in Fig. 10) which corresponds to the trap ionization energy (given as input to the simulator).This confirms that it is the emission of electrons from donor traps that determines the V T decrease.As a matter of fact, when emitting electrons, donor traps become positively charged thus reducing the effective p-body doping and decreasing V T (i.e., ΔV T < 0 V).
Generally, having relatively low formation energy, nitrogen vacancies (V N ) act as compensating donor impurities in p-type GaN [33].However, V N transition energy is reported to be shallower than 1 eV [33].Other defects with donor-type behavior and transition energies that can be associated with the 1-eV trap experimentally observed in this article are (defects are ordered from lowest to highest formation energy under p-type growing conditions): nitrogen interstitial (N i ); gallium interstitial (Ga i ); and gallium antisite (Ga N ) [33].
To quantify the ramifications of V T instability in a practical scenario, we performed a mixed-mode, circuit/device simulation of a 36-12 V buck converter including the TMOS simulated at the device level.
Voltage and current at transistor terminals are obtained from the self-consistent solution of the circuit and drift-diffusion Simulated dissipated power by the TMOS during switch-ON, ON-state, and switch-OFF.Switching period is 20 μs.The origin on the x-axis corresponds to 3 ms, i.e., after 150 cycles from simulation start to ensure switching regime conditions are reached.The two curves correspond to the fresh TMOS (blue line) and the stressed TMOS with increased V T (red curve) of 4.7 V, corresponding to the worst-case as obtained from experimental data in Fig. 4(a).equations within the external network and within the TMOS itself, respectively.The passive elements of the LC low-pass filter are ideal, as well as the diode except for its forward-bias voltage drop.
Fig. 11(a) shows the circuit schematic and Fig. 11(b) shows the dissipated power by the TMOS during switch-ON, ON-state, and switch-OFF, in steady-state regime for two cases, namely: the unstressed TMOS (i.e., ΔV T = 0 V) and the stressed TMOS with ΔV T = 4.7 V corresponding to the worst-case as taken from experimental data in Fig. 4(a).As it can be seen from Fig. 11, V T increase negatively impacts both switching and Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.conduction losses.The increased losses in the buck converter with the degraded TMOS lead to a reduction of the efficiency from about 84% to 78%.

VI. CONCLUSION
We evaluated the threshold voltage instabilities induced by the application of OFF-state bias in vertical GaN TMOS's.V T was found to increase during application of the OFF-state stress bias and recover with a process that is accelerated by temperature with ≈1-eV activation energy (E A ). Vertical p-n diodes fabricated on the same wafer were also characterized and it was found that the depletion capacitance was also subjected to changes following the application of a reverse bias and accelerated by temperature with the same E A as V T recovery in TMOS devices.This indicates that the source of these instability is related to traps in the epitaxial layer.These observations were corroborated by numerical simulations showing that including donor traps in the p-type body layer at 1-eV from GaN conduction band edge allows both V T and C DEP instabilities to be reproduced.Specifically, V T instability in TMOS is determined by the modulation of the effective p-type doping density, while C DEP increase in the p-n diode is due to the decrease of the effective depletion layer width.The experimental conditions employed in this article are such that the results regarding V T instability are relevant information for both device engineers as well as application engineers.

Fig. 2 .
Fig. 2. Schematic cross-section of the (pseudo) vertical GaN devices under study in this article.(a) Trench MOSFET.(b) p-n diode.Devices share the same epitaxy.

Fig. 4 .
Fig. 4. Analysis of V T instability during OFF-state stress by means of fast V T transient characterization.Typical I D -V GS curves in (a) stress (V DS,STR = 30 V) and (b) recovery (V DS,REC = 0 V) conditions.(c) and (d) ΔV T transients extracted during stress and recovery, at different V DS,STR (see legend).

Fig. 5 .
Fig.5.Analysis of the OFF-state V T transients as a function of different V DS,STR and V GS,STR (see legend).The increase of V T is strongly dependent on V DS,STR and negligibly affected by V GS,STR .

Fig. 6 .
Fig. 6.Drain and gate leakage current during the step-stress experiment.

Fig. 7 .
Fig. 7. V T transients acquired while applying V DS = 0 V after 100-s stress at V DS,STR = 30 V. (Inset) Arrhenius plot extracted from the data.

Fig. 8 .
Fig. 8. C-ITS capacitance transients detected on p-n diodes at different temperatures, while keeping V R = -30 V. Dashed lines are C DEP fitting curves with stretched exponentials from which the time constants (τ 's) are obtained.(Inset) Arrhenius plot extracted from the τ 's.

Fig. 9 .
Fig. 9. Simulated C-ITS capacitance transients on p-n diodes at different temperatures, while keeping V R = -30 V, under different modeling assumptions: traps included in (a) body only, (b) drift only, and (c) both in body and drift regions.Dispersion in case (a) More closely agrees quantitively with experimental data fitting curves corresponding to the part of the transients attributed to carrier emission, reported in the inset for easier comparison.

Fig. 10 .
Fig. 10.Simulated V T transients acquired while applying V DS = 0 V starting from an initial condition with completely filled donors in the p-type region.(Inset) Arrhenius plot extracted from the simulation data.

Fig. 11 .
Fig. 11.(a) Circuit schematic of the simulated 36-12 V buck converter.(b)Simulated dissipated power by the TMOS during switch-ON, ON-state, and switch-OFF.Switching period is 20 μs.The origin on the x-axis corresponds to 3 ms, i.e., after 150 cycles from simulation start to ensure switching regime conditions are reached.The two curves correspond to the fresh TMOS (blue line) and the stressed TMOS with increased V T (red curve) of 4.7 V, corresponding to the worst-case as obtained from experimental data in Fig.4(a).