NPL.H: Neutral-Point-Less H-Type 3-Level Inverter

This article introduces a neutral-point-less H-type (NPL.H) 3-level dual inverter topology for motor drive applications. This multilevel topology craftily eliminates the neutral clamp and neutral point current altogether, resulting in a drastically lower minimum dc-link capacitance, compared with conventional 3-level inverter topologies, while retaining the multilevel benefits. NPL.H has additional merits, including lower output harmonics, lower current stress, and lower capacitor current ripple. The topology is optimal for balanced 6-phase, dual 3-phase, or 3-phase open-end winding motors. This article proposes a low-order frequency form (LoF) for fast and accurate calculations of the important circuit variables (e.g., rms currents of switching devices, inverter bridge input, and dc-link capacitor, and the voltage ripple of the dc-link capacitor), and demonstrates an example in detail with the sinusoidal pulsewidth modulation. Many practical design parameters (e.g., dead time) are reflected in our method to enhance the accuracy of the analytical model. The theoretical rms current expressions of NPL.H are successfully derived via LoF. Through simulation and experiment, we validate the precision and effectiveness of LoF as well as the strengths of the NPL.H topology. Our NPL.H can eliminate at least 75% of the dc-link capacitance of the conventional T-type 3-level topology while maintaining the same voltage ripple performance under otherwise same operating conditions, and up to 73% compared with the traditional 2-level inverter. Our new NPL.H topology unlocks a significantly higher power density for electric transportation and other high-power applications, where the size of a dc-link capacitor bank has traditionally been a major blockade for a high power density.

Abstract-This article introduces a neutral-point-less H-type (NPL.H) 3-level dual inverter topology for motor drive applications.This multilevel topology craftily eliminates the neutral clamp and neutral point current altogether, resulting in a drastically lower minimum dc-link capacitance, compared with conventional 3-level inverter topologies, while retaining the multilevel benefits.NPL.H has additional merits, including lower output harmonics, lower current stress, and lower capacitor current ripple.The topology is optimal for balanced 6-phase, dual 3-phase, or 3-phase open-end winding motors.This article proposes a low-order frequency form (LoF) for fast and accurate calculations of the important circuit variables (e.g., rms currents of switching devices, inverter bridge input, and dc-link capacitor, and the voltage ripple of the dc-link capacitor), and demonstrates an example in detail with the sinusoidal pulsewidth modulation.Many practical design parameters (e.g., dead time) are reflected in our method to enhance the accuracy of the analytical model.The theoretical rms current expressions of NPL.H are successfully derived via LoF.Through simulation and experiment, we validate the precision and effectiveness of LoF as well as the strengths of the NPL.H topology.Our NPL.H can eliminate at least 75% of the dc-link capacitance of the conventional T-type 3-level topology while maintaining the same voltage ripple performance under otherwise same operating conditions, and up to 73% compared with the traditional 2-level inverter.Our new NPL.H topology unlocks a significantly higher power density for electric transportation and other high-power applications, where the size of a dc-link capacitor bank has traditionally been a major blockade for a high power density.

I. INTRODUCTION
T HE dual three-phase inverters have become one of the mainstream research topics due to the increasing demands in high-power medium-voltage motor drive applications, such as electric vehicles (EVs) [1], railway traction [2], elevator, aerospace [3], and electric naval propulsion [4].Compared with traditional single three-phase inverters, the dual versions have the advantages of lower current stress, lower dc-link capacitor current/voltage ripples, higher power density, improved fault-tolerant capability, and lower torque harmonics for both dual three-phase motors or single three-phase open-end winding (OEW) motor applications [5], [6], [7], [8], [9], [10], [11], [12], [13], [14].Meanwhile, the three-level (3 L) inverters are also drawing increasing attention for large-capacity medium-voltage applications, as they improve output voltage quality, reduce device voltage stresses, reduce conduction and switching losses, and enhance a fault tolerance [15], [16], [17], [18].The combination of a 3 L inverter and a dual three-phase structure can further improve a motor drive's overall performance and reliability.
A dual three-phase motor drive based on two sets of independent T-type 3 L inverters is proposed in [19].The dc-link capacitor voltages are well balanced in both steady-state and transient conditions.In addition, the current flow through the dc-link capacitors is reduced due to the interleaved modulation strategy.Nevertheless, the number of switches, the size, and the overall cost are greatly increased compared with two-level inverters.The authors in [20] and [21] introduced 3 L dualoutput inverters based on the neutral-point-clamped (NPC) 3 L inverter to reduce the number of switches in comparison with the conventional two 3 L inverters.However, the switching modes are limited, and the neutral point voltage is difficult to be balanced [20].In [21], a new topology was formed by adding eight switches and six clamp diodes for a lower neutral current and a better neutral point voltage balancing.However, not only has the number of switches increased, complicating the modulation but also the neutral point current and voltage fluctuations cannot be sufficiently suppressed, necessitating the presence of a large dc-link capacitance.
This article introduces a neutral-point-less H-type (NPL.H) 3 L dual inverter topology for motor drive applications.In addition to the aforementioned benefits (i.e., lower minimum dc-link capacitance, retained multilevel benefits, lower output harmonics, lower current stress, and lower capacitor current ripple), NPL.H also eliminates the necessity of the voltage balance among dc-link capacitors in a traditional multilevel inverter topology.This article has three main contributions.
First, this article presents a neutral-point-less multilevel inverter topology and includes analytical derivations of a dc-link capacitor's voltage and current ripples for the first time.A ripple performance analysis has traditionally played a vital role in evaluating the performance of an inverter, designing parameters, and selecting appropriate devices [22], [23], [24], [25], [26],  [27], and are particularly emphasized in multiphase motor drive applications, such as EVs, where the volume, weight, cost, and reliability are of crucial importance.These statements are still true with the proposed inverter.However, the new topology no longer has a neutral point current, which, in existing topologies, has been the primary element that drives the capacitor-related calculations and decisions.The neutral point current often has an overpowering impact such that all the other current entities associated with the dc-link capacitor can be simply ignored during the derivation.In our new topology, the nonexistence of the neutral point fundamentally reshapes the mathematical landscape and necessitates a new derivation of ripple performances.
Second, an accurate low-order frequency form (LoF) for analyzing various circuit variables is created to serve as a numerical model.This LoF approach-essentially a switching period equivalent root-mean-square (rms)-transforms an unmanageably long chain of obscure switching frequency calculations into a drastically short and intuitive analysis at a much lower ac frequency.LoF is used for the calculations of the device rms current, inverter bridge input rms current, dc-link capacitor rms current, and dc-link capacitor voltage ripple.For conventional two-level three-phase inverters, the rms value of the dc-link capacitor current is calculated in the time domain at the switching frequency [28], [29], [30], and the inverter input current is obtained by the switching functions and output phase currents.In [31] and [32], the double Fourier integral-based method is adopted to demonstrate the dc-link current harmonics for unconventional pulsewidth modulation (PWM) strategies.Recent publications [33], [34], [35] explored rms current and voltage ripple calculations for multilevel and multiphase inverters using various methods.However, to the best of the authors' knowledge, there is no published work on accurate modeling and analysis from the perspective of low-order frequencies, and no intuitive and concise calculation formulae that show influential variables and their impacts on ripples have been obtained.
Finally, our ripple performance analysis and formulae are comprehensive, including many practical and influential factors in the modeling process (e.g., power factor angle, modulation index, switching frequency, output power/current rating, and dead time.), and highly accurate.This is especially beneficial for wide bandgap applications.For example, while the antiparallel diode's reverse recovery is well known and must be accounted for insulated-gate bipolar transistor (IGBT) devices [36], that for silicon-carbide (SiC) field-effect transistors (FETs) is almost negligible.In contrast, a dead time must be considered in ripple calculations for SiC applications, as opposed to for IGBT applications, due to a higher switching frequency.The comparison  II.It is evident that our NPL.H can eliminate at least 75% of the dc-link capacitance of the conventional dual NPC 3 L and dual T-type 3 L topologies and reduce the total number of switches required while maintaining the same voltage ripple performance under otherwise same operating conditions, and upto 73% compared with the 2-level inverter.NPL.H unlocks a significantly higher power density for electric transportation and other high-power applications, where the size of a dc-link capacitor bank has traditionally been a major blockade for a high power density.
The rest of this article is organized as follows.First, the topology and operational principle of the proposed NPL.H are introduced in Section II.Section III presents the switching period equivalent rms current concept, referred to as the LoF.LoF of the inverter rms currents and voltage ripple, considering the dead-time effect, are also obtained.Section IV provides the simulation verification of the proposed LoF for various rms currents and voltage ripple calculations.Section V presents the discussion on ripple performance of NPL.H and its implication on dc-link capacitance.Section VI presents the experimental results under various inverter operating conditions and a comprehensive comparison against calculation and simulation.Finally, Section VII concludes this article.

II. TOPOLOGY AND OPERATIONAL PRINCIPLE OF NPL.H
The proposed NPL.H topology is shown in Fig. 1.It is composed of six half-bridge legs and three interphase commutation legs.The six half-bridge legs are constructed with two conventional three-phase 2-level inverters.The three interphase legs are added in to provide commutation paths and generate the 3 L output voltages.The dv/dt and output voltage harmonics of  NPL.H are, therefore, naturally reduced.The voltage from the midpoint of each half-bridge leg to ground in NPL.H can be V dc , V dc 2 , or 0. Hence, the line-to-line output voltage in NPL.H can be +V dc , + V dc 2 , 0, − V dc 2 , or −V dc .Furthermore, no switch current is injected to or extracted from the midpoint of the dc-link capacitors, thereby significantly reducing the dc-link voltage ripple.NPL.H has a great merit for dual-motor applications as the required capacitance and overall volume of the dc-link capacitors can be greatly reduced, compared to existing inverters for dual-motor applications [5], [6], [7], [8], [9], [11].
The modulation waveforms and gate signals for NPL.H are presented in Fig. 2. The sinusoidal pulsewidth modulation (SPWM)-based phase disposition modulation technique is adopted here [37].M A , M B , and M C are the modulation waveforms for the dual three-phase legs.As shown in Fig. 2, the switch pair S A1 and S A4 have the same PWM signal, and so do the pairs S A2 and S A3 , S B1 and S B4 , S B2 and S B3 , S C1 and S C4 , and S C2 and S C3 .The gate signals of switches S A6 , S A5 , S B6 , S B5 , S C6 , and S C5 are complementary to the gate signals of switches S A1 , S A2 , S B1 , S B2 , S C1 , and S C2 , respectively.According to the modulation waveforms above, there is a 180 • phase difference between two sets of three-phase output voltages in NPL.H (e.g., 1, 4, and 6 versus 2, 3, and 5).When a balanced load is connected to an inverter phase, NPL.H will have two sets of three-phase currents with the same value in the opposite directions.
Three different switching states of one H-leg are shown in Fig. 3. "[P]" denotes a state where the top switch of the upper inverter, the bottom switch of the lower inverter, and one switch of the interphase are turned on while other switches are turned OFF.The terminals A 1 and A 2 are connected to the positive dc-bus (P) and negative dc-bus (N) with voltages of +V dc and 0, respectively."[O]" denotes a state where the two switches of the interphase are turned on while other switches are turned OFF.In this state, A 1 and A 2 are essentially shorted.Assuming the inverter operates with balanced three-phase loads, the voltage of A1 and A2 will be clamped to + V dc 2 by the load impedances, resulting in the generation of the same voltage potential of + V dc 2 ."[N]" denotes a mirrored case of "[P]," where A 1 and A 2 are at 0 and +V dc , respectively.This clearly generates three voltage levels in one H-leg: V dc ; V dc 2 ; and 0. A total of 27 switching modes with 3-phase H-legs are characterized and summarized in Fig. 4. The switching modes are further divided into five groups based on a combination of their phase output voltages in Table III.The switching modes [P P P], [O O O], and [N N N] can serve as zero vectors, providing zero line-to-line voltages for both inverters.As expected, the line-to-line voltages generate five output voltage levels: +V dc ; + V dc 2 ; 0; − V dc 2 ; and −V dc .

III. ANALYTICAL MODELING OF LOW-ORDER FORM RMS CURRENTS AND DC-LINK CAPACITOR VOLTAGE RIPPLE
In this section, analytical expressions for the inverter bridge input rms current, dc-link capacitor rms current, and dc-link Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE III SWITCHING MODES AND AC VOLTAGES OF NPL.H INVERTER
voltage ripple are derived assuming SPWM.The two output loads of NPL.H are assumed to be balanced here.The traditional switching frequency-based calculation method is simplified and the low-order form calculation formulae of the rms currents and ripple voltage are derived with considering the effects of different variables, such as dead time.The rms currents and voltage ripple expressions of the traditional dual three-phase 2-level inverter are also derived by the proposed low-order form method for verification.

A. Low-Order Form Analysis for Inverter Switch rms Current
An accurate calculation of the current of a power transistor is crucial in design and analysis of an inverter.The peak current of the transistor-or switch-is normally in a good agreement with the amplitude of the fundamental ac current.However, because of the facts that the switch current is operating at the switching frequency and that the dead time exists in switching patterns, the calculation of its rms current is not straightforward.Fig. 5 shows the current of NPL.H's upper switch as an example.
The switch current of phase A1's upper switch, S A1 , can be expressed by the product of the switching function and phase A1 output current, as shown in (1).The switch rms current can be, therefore, calculated according to the rms definition over one ac cycle.This calculation method is accurate, but complex and not intuitive given that the switching frequency is much higher than the fundamental ac frequency Here, S A1 is the switching function, I ac is the amplitude of the ac current, ω is the grid angular frequency, and θ is the phase angle of the ac current with respect to the ac voltage.The low-order form method for a switch rms current calculation creates a low-frequency waveform that offers an rms equivalent switch current at each high-frequency cycle, as shown in Fig. 6.Once obtained, it dramatically decreases the calculation and simplification overhead as the convoluted expressions from the rms calculation at the switching frequency disappear.
Fig. 6(a) shows an example of a switch current in one switching period, defined as where I a is the current value when switch is turned ON, T sw is the switching period, and D is the duty ratio of the switch.The rms value i sw_rms of the switch current in Fig. 6(a) can be derived as where M is the modulation index, D T d is the duty ratio of the dead time in one switching period (i.e., T dead T sw ), and T dead is the duration of the dead time.
As a result, the switch current in Fig. 5 can be equivalent to the low-order form rms current, as shown in Fig. 6(b).Accordingly, the low-order forms of the rms currents of six upper switches S A1 , S A3 , S B1 , S B3 , S C1 , and S C3 in NPL.H can be derived as and Here, the definitions on the ac currents and modulation functions are The low-order forms of the rms currents of six upper switches under the unity power factor condition are shown in Fig. 7.
Even though the ac currents are considered purely sinusoidal in (7) and (8), the harmonics can be included in this method for more accurate results without any limitation.Furthermore, the rms currents of lower switches and interphase switches of NPL.H can be calculated as Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

and ⎧ ⎨
⎩ Considering that the switch currents may have a positive or negative polarity with a nonunity power factor, the absolute function is applied to the ac currents in ( 5), ( 6), (10), (11), and (12).The switch rms currents in NPL.H can be obtained by simply integrating the square of above equations in one fundamental ac period and taking the square root.Similarly, the low-order expressions of the switch RMS currents for the dual three-phase 2-level inverter can be derived as and Here, i T A1 through i T A4 , i T B1 through i T B4 , and i T C1 through i T C4 are the RMS currents of respective phase switches in dual three-phase 2-level inverter.

B. Low-Order Forms of Inverter Bridge Input RMS Current and DC-Link Capacitor RMS Current
The inverter bridge input RMS current and dc-link capacitor RMS current are crucial for the efficacy analysis and performance evaluation of an inverter and dc-link capacitor design.The instantaneous bridge input current is the sum of all switch currents connected to the top node The switching cycle rms current is then The instantaneous dc-link capacitor current is ) where I dc is the dc input current.The switching cycle rms of it is Due to the three-phase structure, the inverter bridge input current and dc-link capacitor current have the periodicity of 1 6 fundamental period (T ac ).Therefore, the following analysis and calculation will be carried out in the unit of T ac 6 .In the time interval t = [0, T ac /6], NPL.H's inverter bridge input current is 18) and ( 20) are, respectively, simplified to and where A, B, and C are defined as The switch rms currents in (23)'s A are individually calculated in the previous section, and the low-order form rms current expressions of all switches are presented in ( 5) and ( 6).In addition, C in (23) can also be readily calculated by the corresponding ac currents and modulation functions-essentially equivalent duty ratios.The remaining challenge is to calculate B in (23).As it involves multiplications of two switch currents, the detailed analysis on NPL.H's upper switch currents and duty ratios are required, considering their piecewise characteristics during an ac cycle, to create the low-order form.
There are three different combinations for any two upper switch currents, as depicted in Fig. 8.Although the upper switch currents may have a positive or negative polarity under nonunity power factor conditions, it can be shown that the polarities of the switch currents do not affect the validity of the analysis and calculations here.For simplicity, the currents in Fig. 8 are all drawn with a positive polarity.First of all, a combination of two upper switch currents can be divided into three cases.Case 1 in Fig. 8(a) shows the waveforms where the two switch currents are from the same inverter.Cases 2 and 3 in Fig. 8(b) and (c), respectively, are the waveforms with currents from different inverters.
To calculate the integral of sum products of currents in "B" of (23), the current waveforms in each case of Fig. 8 will be subject to the integral The effective duty ratio of Case 1 is determined by the smaller duty ratio, D 2 .For Case 2 The effective duty ratio of Case 2 is (D 1 + D 2 − 1) and depends on the duty ratios of both switches.On the other hand, the calculation result for Case 3 is always 0, as the two currents do not overlap in time.This occurs when the two currents are from different inverters and D The modulation waveforms of the switches S A1 , S C1 , and S B3 during t = [0, T ac /6] are shown in Fig. 9 as red, green, and  blue curves, respectively.The black curve denotes 1 − |M B | and can be used to calculate the range and boundary points of Case 3. The time points, t A and t B , corresponding to boundary points A and B in Fig. 9, can be calculated as Table IV gives different time ranges and corresponding case designations for the calculation of the integral of interest, i a i b dt T sw , in the 1  6 fundamental period.Based on this table, the calculation of B in ( 23) can be completed.
Once A, B, and C of ( 23) are obtained, the simplified loworder form of the inverter bridge input rms current, (21), and dc-link capacitor rms current, (19), can be calculated as Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply. and The proposed low-order form method can also obtain the dual two-level inverter's bridge input and dc-link capacitor RMS currents.The end results are and Here, "2 L" at the end of the subscripts designates that these are the results for the dual three-phase 2-level inverter.Please note that as the steps are nearly identical to NPL.H's, the detailed derivation is omitted, and the end results are directly provided.Equations ( 27) and ( 28) now clearly and intuitively express the impacts of the practical design variables, I ac , M , θ, I dc , and D T d , on the inverter bridge input rms current and dc-link capacitor rms current.Different parameter values and/or operating conditions can be easily calculated with ( 27) and (28) for a new design.Analysis and evaluation of an existing design can be directly performed with our equations as well.

C. Low-Order Form of DC-Link Capacitor Voltage Ripple
The dc-link capacitor voltage ripple is closely related to the dc-link capacitor current and is an important basis for a determination of a dc-link capacitance.Like the dc-link capacitor current, the dc-link capacitor voltage repeats every 1   6   fundamental period.
To analyze and calculate the dc-link capacitor voltage ripple, different types of dc-link capacitor currents and voltages are illustrated for the time interval of t = [0, T ac /6] in Fig. 10.Here, since the switching frequency normally is much larger than the ac frequency, the switch current is considered constant within one switching cycle.Note that with the modulation shown in Fig. 2, there are three upper switches conducting currents at any switching cycle in one ac period.There are eight combinations based on the polarities and duty ratios of the three switch currents.The three switch currents are labeled as I sw1 , I sw2 , and I sw3 in Fig. 10.Among these three, two currents always come from the upper switches of the same inverter and the other from the upper switches of the other inverter.In addition, with the power factor angle from − π 2 to + π 2 , at most two currents have negative polarities at the same time, and they must be from the upper switches of different inverters.
An examination of these plots reveals that the amplitude of the dc-link capacitor voltage ripple in one switching cycle for all types can be determined by considering only two ascending/descending time periods, t = [t 0 , t 1 ] and t = [t 6 , t 7 ], which are highlighted in yellow.During these two time periods, only one switch current exists for all types, and the dc-link capacitor voltage increases monotonically.The dc-link capacitor voltage ripple in 1  6 ac period is derived as (31) According to the modulation waveforms during t = [0, T ac 6 ] in Fig. 9, the duty ratio relationship of the three switches are ⎧ ⎨ ⎩ t = 0, T ac 12 : Therefore, during t = [0, T ac 12 ], the Δt is (34) By substituting (33) and ( 34) into (31), the envelope of the dclink capacitor voltage ripple is obtained as a function of inverter parameters.If the dc-link capacitance is designed based on a dc-link capacitor voltage ripple requirement, the design criterion of the capacitance is where 0 ≤ t ≤ T ac 6 .

TABLE V NPL.H PARAMETERS FOR SIMULATION
Meanwhile, the dc-link capacitor voltage ripple of the dual 2-level inverter can be derived as where ΔV Cdc_pp_2 L refers to the dc-link capacitor voltage ripple of the dual three-phase 2-level inverter and Δt 1_2 L and Δt 2_2 L are the new ascending/descending time period defined as and i ac are the related ac phase currents in the time interval of (39)

IV. SIMULATION VERIFICATION
In this section, a simulation model for NPL.H is built in PSIM software to verify the effectiveness of the proposed low-order form method and validate the calculation of the rms currents and voltage ripple in the previous section.The main parameters of the inverter model are given in Table V.The line-to-line rms ac output voltage is fixed to 450V rms , ac frequency is 125 Hz, switching frequency is 10 kHz, and dead time in one switching cycle is set to 300 ns.The parameter ranges of the power factor angle (θ), modulation index (M ), and output apparent power (S) are given in Table V.
The dc-link capacitor voltage (V dc-link ), dc input current (I dc ), and ac phase current amplitude (I ac ) can be expressed as The simulated waveforms of NPL.H with the SPWM modulation are presented in Fig. 11.The PWM signals for NPL.H are generated by three modulation waveforms, M A , M B , and M C , and two carrier waveforms, "Carrier 1" and "Carrier 2," shown in Fig. 2. In addition, also shown in Fig. 12 are the simulated waveforms of the inverter output phase voltages, phase currents, input current, inverter bridge input currents, and dc-link capacitor current and voltage.Here, the dc input voltage of 900 V, power factor angle of − π 6 , and output power of 350 kVA are used.
Different operating conditions of NPL.H are further tested in simulation and presented in Fig. 13.The calculation results using the proposed low-order form of the rms currents and voltage ripple are overlaid on top.The simulation results of the inverter bridge input rms current, I inv_in_rms , and the corresponding theoretical calculation results are in excellent agreement under different inverter operating conditions.The base case is the power factor angle (θ) of 0, modulation index (M ) of 0.85, and output apparent power (S) of 350 kVA.Each subplot shows a variation caused by a single parameter.
The simulation and calculation results of the dc-link capacitor rms current, I Cdc_rms , are presented in Fig. 14.Again, they are in excellent agreement.A single parameter variation with the same base case is used for each subplot.calculation results under different inverter operating conditions are still in excellent agreement.A single parameter variation with the same base case is also used for each subplot.
To better evaluate the accuracy of the proposed theoretical calculation model using the low-order forms of the rms currents and voltage ripple, the errors between simulation and calculation results are plotted in Fig. 16.Under different operating conditions, the errors are all less than 3%, thereby proving the effectiveness and excellent accuracy of the proposed analytical model.The ripple performance of NPL.H in the inverter bridge input rms current, dc-link capacitor rms current, and dc-link capacitor voltage is compared with that of the dual T-type 3 L inverter and dual 3-phase 2-level inverter under different operating conditions.Since there is little difference (<3%) between the theoretical calculation results from the derived low-order form expressions and the simulation results, the following comparisons are made based on the simulation.Fig. 17 shows the rms currents and voltage ripple performance of NPL.H and dual 3-phase 2-level inverters at the rated condition used in the previous section (i.e., power factor angle (θ) of 0, modulation index (M ) of 0.85, and output apparent power (S) of 350 kVA).NPL.H shows significantly improved performance, compared with the 2-level inverter, in both dc-link current and voltage ripples.It also provides the same output power at a slightly lower input rms current, owing to its low ripple characteristics.For a Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.the dual T-type inverter under the same inverter operation conditions.Nevertheless, the proposed NPL.H not only has a fewer number of switches but also can greatly reduce the required physical capacitance.Fig. 21 shows the dc-link capacitor bank configurations of NPL.H and dual T-type inverter.Although two inverters require the same overall dc-link capacitance under the same dc-link voltage ripple requirement, the dual T-Type 3 L inverter requires two sets of 2C dc capacitors (i.e., 4 C dc in total) connected in series due to the existence of neutral points, while NPL.H only needs one set of C dc capacitors (i.e., 1 C dc in total).Therefore, NPL.H reduces the required physical capacitance-hence physical volume as well-to 25% of the capacitance required by the dual T-type 3L inverter.To assess the performance of the analytical method for rms currents and ripple voltage, the experiments are repeated in different inverter operating conditions.The proposed low-order analytical model is verified by five groups of experimental test cases under different RL load conditions, as given in Table VII.For each experiment, the voltage and current waveforms are recorded, and the analytical calculation method was applied to yield corresponding results of the inverter bridge input rms  Then, the measured inverter bridge input rms currents, dc-link capacitor rms currents, and voltages under different test cases with different power factor angles (θ) and output apparent power (S) are processed, and the corresponding theoretical calculation results are obtained through the proposed low-order form analytical method.The comparison results of experimental results and calculation results are shown in Fig. 24.It can be found that different inverter operating conditions, the experimental results are in good agreement with the theoretical calculation results.
In addition, the errors between the obtained experimental results and theoretical calculation results in Fig. 24    shows detailed error percentages under different test cases.The error between the calculation and experiment is slightly larger than the error between the calculation and simulation.Potential sources of this error are that the experiments are carried out at a smaller scale, resulting in an increased proportion of calculation errors; and the nonidealities that are difficult to quantify, such as magnetic losses, measurement-related errors, turn-ON and turn-OFF, and transient processes of switching devices, are not fully considered.However, the absolute level of the calculation error is still acceptable to show the validity of the proposed low-order form analytical model, as well as the topological superiority of NPL.H.

VII. CONCLUSION
A novel NPL.H 3 L dual inverter topology and an improved analytical model of inverter rms currents and voltage ripple are introduced for motor drive applications, especially those with balanced 6-phase, dual 3-phase, or 3-phase OEW motor configurations.The proposed NPL.H has the advantages of multilevel output, lower output harmonics, lower current stress, fewer power switches, and lower capacitor current and voltage ripples while eliminating the neutral clamp, the neutral point current, and the necessity of capacitor voltage balancing altogether.Moreover, the dc-link capacitance in NPL.H can be reduced by 75% compared with the conventional T-type 3 L inverter, and by upto 73% compared with the 2-level inverter, under the same dc-link voltage ripple requirements.These traits will be the essence of the low-cost and high power density future motor drive systems.
Our concise and highly accurate analytical model for calculating the inverter bridge input rms current, dc-link capacitor rms current, and voltage ripple, including the dead-time effect, is introduced.The low-order form approach is proposed to simplify the calculations at the full switching frequency and can be readily expanded to different inverter topologies and modulation methods.The proposed low-order form calculation method is demonstrated to be more effective and enhanced than the traditional methods, with comprehensive consideration of the influence of different variables.Furthermore, the calculation formulae are simple and straightforward, avoiding the need for switching frequency computation components.This low-order form analysis method has been verified through simulation and experiment under various circuit and design parameters and can be used as a general calculation tool for rms currents and voltage ripple in different inverter topologies.

Fig. 15
presents the comparison of simulation and calculation results of the dc-link capacitor voltage ripple, ΔV Cdc , with 100 μF dc-link capacitance.The simulation and theoretical

Fig. 14 .
Fig. 14.NPL.H DC-link capacitor rms current varies with variables.(a) I Cdc_rms varies with different θ.(b) I Cdc_rms varies with different M .(c) I Cdc_rms varies with different S.

Fig. 16 .
Fig. 16.Error between calculation and simulation results varies with variables.(a) Error varies with different θ.(b) Error varies with different M .(c) Error varies with different S.

Fig
Fig. RMS currents and ripple voltage comparison of NPL.H and dual 3-phase 2-level inverters at rated condition.

Fig. 18 .
Fig. 18.Comparison results of input rms current varies with variables.(a) I inv_in_rms varies with different θ.(b) I inv_in_rms varies with different M .(c) I inv_in_rms varies with different S.

Fig. 19 .
Fig. 19.Comparison results of DC-link rms current varies with variables.(a) I Cdc_rms varies with different θ.(b) I Cdc_rms varies with different M .(c) I Cdc_rms varies with different S.

Fig. 21 .
Fig. 21.Comparison of required physical capacitors between NPL.H inverter and dual T-type 3 L inverter.
are further calculated and drawn in Fig.25.There are three curves, which represent the calculation errors of the inverter bridge input rms currents I inv_in_rms , dc-link capacitor rms currents I Cdc_rms , and dc-link capacitor voltage ripples ΔV Cdc , respectively.Fig.25

Fig. 24 .
Fig. 24.Comparison of experimental results and calculation results under different test cases.(a) I inv_in_rms under different cases.(b) I Cdc_rms under different cases.(c) ΔV Cdc under different cases.

Fig. 25 .
Fig. 25.Error between calculation results and experimental result varies with different test cases.

TABLE I COMPARISON
OF THE PROPOSED LOF ANALYTICAL METHOD WITH EXISTING METHODS

TABLE IV RANGES
AND CORRESPONDING CASES FOR Table VI gives the dc-link capacitance required by the dual T-type 3 L inverter, NPL.H, and dual 2-level inverter under the same operation condition and dc-link voltage ripple requirement.The capacitance reduction percentages for each case are also presented for convenience.According to Table VI, NPL.H can reduce the required dc-link capacitance by at least 40.2% and as high as 73.4% compared with the dual 2-level inverter and by 75% compared with the T-type 3 L inverter.This substantial reduction of the required dc-link capacitance can lead to an unprecedentedly high level of power density.

TABLE VI COMPARISON
RESULTS OF REQUIRED DC-LINK CAPACITANCE FOR NPL.H, DUAL T-TYPE 3 L, AND DUAL 3-PHASE 2-LEVEL INVERTERS