A Differential-Mode Isolated AC/AC Converter

In this article, an isolated single-stage direct power conversion (DPC) type ac/ac converter is outlined. The ac/ac converter is based on differential-mode (DM) architecture where two dc/dc converter modules are connected differentially. The pulsewidth modulation active-clamp-Ćuk converter is used for the DM modules as the converter allows zero-voltage-switching turn-on capability on all switches over a wide operating range, enabling the construction of a high-efficiency ac/ac converter. This article details the modulation scheme and the operational analysis of the new DM ac/ac converter (DMAC). In DPC-type ac/ac converters, the converter is required to propagate the input port electric signal to the output port with minimal internal energy storage. The capacitative component internal to the converter undergoes the ac voltage transition, which appears as a capacitive load resulting in reactive power injection in the input port. Hence, a thorough design process of the ac/ac converter is provided to minimize the internal capacitance of the converter. A 1-kW hardware prototype is also built using the underscored design process to validate and demonstrate the operation of the ac/ac converter.

. Topology classification of isolated AC/AC converters [1]. efficiency offered by LFTs is quite high (> 97% [1]). Hence, development of high efficiency isolated ac/ac converter would bolster the adaptation of SSTs in the power grid systems. The ac/ac converter also finds its application as dynamic voltage regulators (DVR) to compensate for voltage sags and swells caused by sudden change in large loads [5], [6], [7]. DVR are generally deployed for sensitive loads such data centers and hospitals [8].
In [1], the isolated ac/ac converter is classified in four types as also shown in Fig. 1. Type A is a DPC type ac/ac converter configuration that is cheaper, simpler, and offers higher efficiency [9]. Typically, in Type A ac/ac converter the power flow is directly propagated between the input and output port without much conditioning or frequency decoupling. Type B and Type C are two-stage ac/ac converter solutions with one stage as an ac/dc converter and the other as a dc/ac converter stage. Besides the required galvanic isolation, the presence of a dc-link in the two-stage ac/ac converter allows the converter to improve the power quality by using the dc-link for filtering and power decoupling. However, the control of a two-stage converter is more complex, and the implementation requires bigger passive components. The converter also suffers from lower efficiency due to compounded loss of the two stages. Type D ac/ac converter configuration consists of three conversion stages converter [10], [11], ac/dc converter, dc/dc converter, and dc/ac. This configuration is most widely used as it allows more operational flexibility due to decoupling offered by the two dclinks [1]. However, more stage count results in lower efficiency, complex control structure, higher sensor counts, and bulky passive components than the other configuration of isolated ac/ac converters.
The Type A configured ac/ac converter is generally realized using a folding and an unfolding stage to interface the dc/dc converter [1], [12], [13], [14]. Each of these stages requires a minimum of four extra active switches, significantly increasing the device count. For the isolated dc/dc converter stage, soft-switching capable topologies like dual-active bridge (DAB) converter and LLC converter are widely used in isolated ac/ac converter due to their soft-switching capabilities resulting in higher efficiencies. However, since DAB is a voltage-source converter, the input and the output currents of the converter are discontinuous and require bulkier filter capacitors. Complex converter modulation [15], [16] is also required to maintain soft-switching over a wide load condition.
In a DM converter, two dc-dc converter modules are connected differentially to enable 4 quadrant (bipolar voltage and bidirectional current) operation [17]. The absence of folding and unfolding stages in the DM converter reduces device count and the associated loss. In ac/dc or dc/ac applications [18], [19], [20], the modules are connected in series on the ac side to enable 4 quadrant operation while on the dc-side, the modules are connected in parallel. In [21], a nonisolated buck-boost module-based DM (NIBB-DM) ac/ac converter is introduced. Both the modules in the DM converter are always active (emulating continuous modulation scheme) resulting in additional losses due to power-circulation and switching losses.
In contrast, the proposed isolated DMAC, shown in Fig. 2, is modulated under discontinuous modulation scheme (DMS). DMS was introduced for differential mode inverter (DMI) in [19] where hard-switchedĆuk converter was used for the modules. The modulation scheme in [19] used duty cycle of the switches as the control parameter for the inverter operation. The component design of the dc/dc modules is straightforward due to presence of constant voltage at the input port. In this article, DMS is extended for DM ac/ac converter for isolated pulsewidth modulation (PWM) active-clamp (PAC)Ćuk based dc/dc converter modules [22], [23], [24]. The active-clamp circuit in PAC-Ćuk dc/dc modules of the DMAC enables ZVS turn-ON capability on all its switches, thereby significantly reducing the switching losses with only four active switches. The PAC-Ćuk converter also allows continuous-input and continuous-output currents resulting in reduced input and output filter capacitors.
In [22], operational principle of PAC-Ćuk topology for dc/dc converter application is discussed. The operational analysis underscored in the article assumes linear modes of operation of the converter due to sizable internal capacitors for dc/dc converter application. However, in Type A ac/ac converter operation, the 50/60 Hz ac voltage in the input port is required to be reproduced at the output port without any phase delay. Hence, contrary to dc/dc [22], ac/dc [25], or dc/ac [19] converter where the converter absorbs the input and output perturbation, the Type A ac/ac converter and its modules are designed to permeate the 50/60 Hz signal by reducing the filtering caused by the capacitor internal to the topology. Reduction of internal capacitor results in non-linear mode of operations and in turn deviation from the linear model for PAC-Ćuk dc/dc converter. In addition, as the internal capacitor of the dc/dc modules undergoes sinusoidal voltage variation resulting in reactive power injection in the input port, a large cumulative internal capacitor would deteriorates the power factor at the input side [14].
In this article, operational analysis and modulation of the DMAC is provided. The analysis captures the nonlinear modes of the PAC-Ćuk converter catering to the ac/ac converter application. Leveraging the analysis, design process of the DMAC is also presented with the objective of minimizing the cumulative internal capacitors while ensuring ZVS turn-ON of all the switches. A 1-kW hardware prototype of the DMAC is also built using the design guidelines to validate the working the DMAC.
In this article, the modulation technique dictating the operation of the modules in DM architecture is provided in Section II. A detailed analysis of the mode of operation of the PAC-Ćuk module is provided in Section III. In Section IV, the design process of the DMAC is discussed in detail to minimize internal capacitance. In Section V, experimental validation of the DMAC converter is provided. A comparison of the proposed ac/ac converter with other recent publications is also provided in Section V. Finally, Section VI concludes this article

II. ARCHITECTURAL OPERATION OF THE DMAC
The proposed single-stage DM ac/ac converter consists of two identical isolated PAC-Ćuk dc/dc modules (Module A and Module B) connected differentially as shown in Fig. 2. A PAC-Ćuk dc/dc module contains two auxiliary capacitors C t1 and C t2 , two blocking capacitor C b1 and C b2 , series inductor L r , isolation transformer and switches S 1 − S 4 for module A and S 5 − S 8 for Module B. The two modules are operated similar to DMS introduced in [18] and [19] for dc/ac and ac/dc operation.
The DMS devised for dc/ac converter in [19] dictates that one of the two differentially connected modules stays inactive while the other module is responsible for transferring the required power depending on the ac side polarity. A similar principle is employed for the proposed DMAC. In the DMAC, as both the modules are connected in differential series configuration, the module should maintain current continuity even when one of the modules is not transferring any power, as shown in Fig. 3(a). In the DMS modulation for ac/ac converter, the module modulation should ensure that the inactive module is conducting from both input and output side while the active module is transferring the power to maintain the current continuity. As the output side voltage follows the input voltage v in in Type A ac/ac converter, the active module is dictated by the polarity of v in . The switches of the active module are operated normally at switching frequency while switches in the inactive module are at a fixed state such that the inactive module is maintaining current continuity.
During the positive line cycle (v in > 0), Module B is inactive as S 5 and S 7 are kept turned ON for the positive line cycle and do not take part in power transfer, as shown in Fig. 3(b). As S 6 and S 8 are always complementary to S 5 and S 7 , respectively, they are kept turned OFF. While S 1 − S 4 of Module A are operated with a 50% duty cycle at switching frequency f sw with a phase-shift ratio, Δ φ defined as the ratio of the time delay of turn on of S 3 with respect to S 1 to switching period T s , to control the power flow. During the negative line cycle (v in < 0), S 1 and S 3 are kept turned ON for the negative line cycle. S 2 and S 4 are always complementary to S 1 and S 3 , respectively, are turned OFF. While S 5 − S 8 of Module B are operated at 50% duty cycle at switching frequency f sw with a phase-shift ratio Δ φ .

III. MODULE OPERATION OF THE DMAC
In the previous section, the modulation scheme of the two modules is discussed. In this section, the operation principle of the dc/dc modules for the positive input voltage over a switching cycle is described, as shown in Fig. 4. In the figure, the red loop showcases the line frequency current flow and the current continuity formed by the inactive module. Analysis for the negative line cycle is similar to the positive line cycle and, hence, is not described in this article. The results obtained for the positive cycle will be directly applicable to the negative cycle.
The PAC-Ćuk modules designed for the ac/ac converter has significantly smaller capacitors than the PAC-Ćuk dc/dc converter alluded to earlier. The size of the equivalent blocking capacitor, C b is small enough that the ripple across the capacitor cannot be ignored resulting in nonlinear series inductor current in contrast to the dc/dc converter designed in [22]. Accounting the nonlinearity is important in the analysis as it influences the power transfer equation and alters the maximum power transfer capability of the designed converter. In addition, the ZVS turn-ON region of the switches are also highly dependent upon the series inductor current.
The operation of the DMAC with Module A switching and Module B bypassed is divided into 4 modes of operation in the switching period T s , as shown in Fig. 4. The waveform associated with the modes is illustrated in Fig. 5. In this article, the small-case variable represents a time-varying variable whereas a capital-case variable is used for the timeinvariant variable and parameter. The following assumptions are made to illustrate the operation and analysis of the proposed converter.
1) All the switches (S 1 − S 8 ), capacitors, and magnetic components are assumed ideal. The switches associated with the active module are operated at a 50% duty cycle. The  output capacitance of the switches is assumed insignificant. Hence, the turn-OFF transition of the switches is ignored in the mode analysis as the duration of the switching transition is small compared to the duration of the modes [26].
2) The transformer turn ratio of n : 1 is considered. The magnetizing inductance of the transformer is considered much higher than the series inductance. Hence, the two blocking capacitors C b1A and C b2A can be lumped into an equivalent blocking capacitor C bA = C b1A C b2A n 2 referred to the input side of the transformer.
3) The switching voltage ripple on the auxiliary capacitors is maintained small enough that it can be assumed constant over a switching cycle in the analysis. In PAC-Ćuk dc/dc converter module, the power is transferred from the input port to the output port using the voltage applied across the high-frequency (HF) link formed by L rA , C b1A , and C b2A , as shown in Fig. 4 by the blue highlight loop. The voltage across the HF-link is given by the difference between v 1 which is the voltage across S 1 and v 2 , which is the voltage across S 3 . The current flowing into S 1 and S 2 is denoted by i 1 while the current flowing into S 3 and S 4 is denoted by i 2, as shown in Fig. 4. Current i 1 and i 2 is given by where i LinA and i LoA are the input and output inductor current while i LrA is the series inductor current of Module A. As the duty cycle of the switches is fixed at 50%, the average voltage across the capacitor is found using the voltage-second balance where is the operator used to denote the average value over a switching period, T s and v CbA is the equivalent voltage across the capacitors when the circuit is referred to the input side. The circuit is assumed to be in a state where S 1 and S 4 are already turned-ON.
The gate of S 2 should be exerted before the polarity reversal of i 1 to achieve the ZVS turn-ON of the switch. The voltage applied across n 2 ), and L rA is positive and is the sum of v Ct1A and nv Ct2A . Using the KVL and KCL in the HF-link loop, the differential equation of i LrA and v CbA is given by Solution of i LrA and v CbA for this mode is obtained as follows: where Z r is the resonance impedance and ω r is the resonance frequency given by The gate of S 3 is applied before the polarity reversal of i 2 to achieve the ZVS turn-ON of the switch. During this mode, the voltage applied across C bA and L rA is v Ct1A . The differential equation of i LrA and v CbA is given by Solution of i LrA and v CbA for this mode is obtained as follows: Mode 3 [t 2 , t 3 ]: At t 2 , S 2 is turned off diverting i 1 to S 1 resulting in internal diode conduction. The gate of S 1 is applied before the polarity reversal of i 1 to achieve ZVS turn ON of the switch. During this mode, the voltage applied across C bA and L rA is zero. The differential equation of i LrA and v CbA is given by Solution of i LrA and v CbA for this mode is obtained as follows: The gate of S 4 is applied before the polarity reversal of i 2 to achieve ZVS turn ON of the switch. During this mode, the voltage applied across C bA and L rA is. The differential equation of i LrA and v CbA is given by Solution of i LrA and v CbA for this mode is obtained as follows: The solution of the modes requires initial conditions of i LrA and v CbA for all the modes. The closed-form solution of these nonlinear modes is complex, hence, additional simplification is required. As the duty cycle of the switches is 50%, leveraging the symmetricity of i LrA and v CbA following relation of the initial conditions can be obtained Using solution of i LrA and v CbA for the modes and relation given by (21), i LrA (t 0 ) and i LrA (t 1 ) are found as As the output power contribution from the inactive module is zero, only the output power transfer from the active module is required to find the power dependency on Δ φ . Hence, the total power transferred is equivalent to the power transferred into the capacitor C t2A by i LrA over a switching cycle. As i LrA is flowing through C t2A only in mode 1 and mode 4, the power relation is given by Substituting (3), (7), (20), and (21) into (23), a closed-form solution of instantaneous output power is obtained after simplification and given by Equation (24) provides the output power as a function of the control parameter (Δ φ ) and design parameters (ω z , Z r , T s ) where ω r and Z r are depended upon C b1A , C b2A , and L rA .

IV. DESIGN GUIDELINES OF KEY COMPONENTS FOR THE DMAC
In this Type A ac/ac converter solution, the capacitors internal to the topology follow the input and output voltage profile resulting in a capacitive load seen at the input terminal of the converter. The capacitive current drawn by the converter is responsible for charging the internal capacitor and satisfy the relation given by (3). Capacitive loading results in reactive power injection into the input source and reduces the power factor for resistive load at the output of the DMAC. Lower reactive power injection reduces the circulating current and conduction loss. In this section, the process to design the DMAC for the required power range is discussed using the analysis from the previous section while ensuring ZVS turn-ON conditions on all the switches.
A 1 kW ac/ac converter is designed in this section to illustrate the design process. The specification used for the design is given in Table I. As both the dc/dc modules are identical, the design process in this section applies to both modules. Hence, the module subscript is dropped while addressing the components.
The transformer turn ratio, n is determined based on nominal input and output voltage as given by where r = ΔI I is the ripple current ratio [27]. For this converter, r = 0.5 is used to select L in and L o .
Series inductor L r and blocking capacitor C b : The highfrequency resonance link formed by the blocking capacitor and inductor is responsible for transferring power from the input to the output side. As discussed in Section III, the output power of the PAC-Ćuk converter depends on Δ φ , L r , and C b . The resonance parameters, L r and C b should be designed such that the converter allow transfer of the desired minimum and maximum output power with the specification given in Table I. Using (23), the rms output power transfer for resistive load is given by (27). By solving (27) for specification given by Table I, required L r and C b relation is obtained to deliver 1 kW output power for various Δ φ , as shown in Fig. 6. The required capacitor and series inductor have inverse relation for fixed operating point. A smaller capacitor requires a larger inductor for the same output power and Δ φ . On the other hand, a smaller Δ φ at the rated output power allows selection of smaller resonance link In the ac/ac converter design, the capacitor needs to be minimized to limit the reactive power injection by the converter. From Fig. 6, C b = 0.5 μF allows a balanced solution for L r . Reducing C b further would require much higher L r , which increases the core size and the conduction loss. Fig. 7 shows the output power dependency on Δ φ for different L r (near point A, B, and C marked in Fig. 6). For L r = 85 μH, the inductor size is small, however, near low load operation the required phase-shift period, Δ φ T s is smaller than the dead time duration. In a phase-shift based modulation, the minimum phaseshift is limited by the dead time and switching transient duration [28], [29], [30] as the converter modes are not clearly defined during the dead time. Hence, Point A ( L r = 130 μF and C b = 0.5 μF) marked in Fig. 6 is selected for the HF-link parameters. L r = 125 μF and C b1 = C b2 = 2 C b = 1 μF is selected for the designed converter. The shaded region in Fig. 7 shows the range of Δ φ for load range 250 W -1 kW.
The designed L r and C b should also ensure the ZVS turn-ON of all the switches. The ZVS turn-on condition requires that negative drain-to-source current is flowing through the switch to be turned ON. From Fig. 4, the current through S 1 and S 2 is i 1 , hence, ZVS turn-ON condition for S 1 and S 2 depends on i 1 . Similarly, ZVS turn-ON condition for S 3 and S 4 depends on i 2 . Using the requirement of negative drain-to-source current, the ZVS turn-ON conditions for the switches are given by ZVS conditions for S 2 and S 3 are easily satisfied in (28) as the input and output inductor current assists in the inequality, whereas conditions for S 1 and S 4 are more critical to satisfy. Using (28) and (22), Fig. 8 showcases the i 1 (t 0 ), i 1 (t 2 ), i 2 (t 1 ), and i 2 (t 3 ) as a function of output power for the selected component parameters and specification given by Table I. As the current at the time instance of switch turn-ON satisfies the inequality given by (28), the ZVS turn-ON is ensured for all the switches of the DMAC for the full operating load range. For example, in Fig. 8(a), i 1 (t 0 ) is always greater than 0 A and monotonously increasing with output power, which indicates that i ds of S 2 is negative before the gating signal is applied. Hence, ZVS turn-ON condition for S 2 is satisfied for full range of load. Similarly, other switches also satisfies the ZVS turn-ON condition as evident from Fig. 8.
Auxiliary capacitors, C t1 and C t2 : The size of C t1 and C t2 is determined using the allowed voltage variation across these capacitors. Only C t1 is taken as an example to illustrate the design process. Current i 1 flows through C t1 when S 2 is conducting (t 0 − t 2 ), as shown in Fig. 9. By using the charge balance equation on the capacitor (Q = CV ), C t1 is given by where ΔV Ct1 is the required maximum voltage variation across the capacitor at full load and t a is time instant when i 1 = 0 A. The minimum C t1 can be obtained by solving (29) for the maximum load condition. The minimum capacitor relation for C t2 can also be obtained similarly. For a 5% peak-to-peak voltage ripple of the average voltage Δv Ct1 , minimum C t1 of 0.33 μF is required. C t1 = C t2 = 0.47 μF is selected for the designed converter. Hence, the peak voltage on the auxiliary capacitor, C t1 is 655 V for 220 V input voltage.

V. EXPERIMENTAL RESULTS
A 1-kW hardware prototype of the DMAC was built based on the design discussed in the previous section. The specifications of the designed prototype are summarized in Table II. As the two PAC-Ćuk modules are constructed identically, Table II is used for both modules. The series inductance of 125 μH is realized using split winding on the high-frequency transformer resulting in the reduced magnetic count. EE 65 N27 core is used for the transformer with 28 turns ON both the primary and secondary sides of the transformer. The input and output inductors are also realized using gapped EE 65 N27 with 36 turns. As the auxiliary capacitor clamps the switch in the PWM active-clamp converter, the peak voltage across the device is same as the peak voltage across the auxiliary capacitors. Fig. 10 showcases the complete experimental setup of the DMAC. The two separate PAC-Ćuk modules can be seen in the figure. Texas instrument's TMS320F28379D controller is used to generate the modulated PWM signals for the DMAC and fed into each module using D-Sub shielded cables. A simple closed-loop PI controller on the output voltage, v o is used to perform the output voltage control, as shown in Fig. 11. The reference output voltage is generated using the phase-locked loop on the input voltage v in and the required rms voltage of the output port. The output of the PI controller is fed to the DMS modulator which bypasses the inactive module as per input voltage polarity, as shown in Fig. 3. It is to be noted that the sensed input voltage can also be directly used to generate the output voltage reference and polarity detection. For variable ac input source Pacific power's 360-AMX is used. The efficiency, THD of the output voltage, and the power factor at the input are measured using Tektronix's PA3000 power  analyzer. The loading of the converter is performed using resistor loads. Fig. 12(a) and (b) shows the operation of the designed hardware prototype at full load and 18% load conditions. In both load conditions, the output voltage can be seen to be following the input voltage while preserving the sinusoidal characteristic of the input port. In the case of full load (45 Ω), the output voltage total harmonic distortion (THD) is observed to be 1.45% while the input current has a power factor >0.99. The measured efficiency at full load and rated input voltage of 220 V rms is 96.96%. In case of 18% load (250 Ω), the output voltage THD is measured to be 2.11% while the input current power factor is 0.85. The input current leads the input voltage for the resistive load, indicating a capacitive reactive power generated by the converter. The measured efficiency of the converter at 18% load condition is 95.01%.  In Fig. 13, drain to source voltages v ds of switches for both the modules of the DMAC is shown. Module A is active (S 1 − S 4 are switching)when the input voltage is positive while Module B is active (S 7 − S 8 are switching) when input voltage is negative for DMS. The v ds of switches follows the input and output voltage as given by (3) and shown in Fig. 3. In Fig. 14(a) , the waveform captures the switching waveforms for the instance when the voltage is near the peak of input voltage while in Fig. 14(b) the instance is near the zero-crossing. In both cases, the ZVS turn-ON of the switches can be observed as the drain to source voltage of the switches is 0 V, before the gate signal is applied indicating ZVS turn-ON across the full line cycle. The ZVS turn-on of S 2 and S 3 is not shown explicitly, however, from Fig. 14, the v ds of S 1 and S 4 is getting clamped to the auxiliary capacitor on removal of gate S 1 and S 4 indicating   Fig. 15 shows the output voltage THD and the input power factor against range of load conditions. The output voltage THD of the converter is maintained below 2.18%. Even at a 10% load condition, the THD is measured to be 2.18%. The power factor of the proposed converter is near unity for the full load condition, however, it degrades as the load is reduced. The power factor trend of Fig. 15 is observed because the converter draws a certain capacitative current (similar to LFTs magnetizing current) to maintain the desired output voltage. As the load is increased at the output, the percentage share of capacitative current drawn  to maintain the output voltage reduces resulting in near unity power factor at the full load condition. The design process discussed in Section IV minimizes the capacitor internal to the topology which in turn reduces the capacitative current for ac/ac application. Fig. 16 shows the measured efficiency versus output power range and input voltage for fixed output voltage. In Fig. 16(a), the peak efficiency of 97.28% is measured at around 50% load condition at the nominal input voltage of 220 V rms , while the measured efficiency at the full load is 97.16%. The efficiency curve is relatively flat across the 35% to 100% load range for the unity gain conversion. The flat efficiency characteristic is generally desired as the converter operates in the full load range. The efficiency drop for low load conditions is due to higher share of voltage dependent losses which are predominently magnetic losses compared to active power delivered at the output.
The proposed ac/ac converter is also operated with wide input voltage variation while maintaining the nominal output voltage to demonstrate voltage regulation capability. In Fig. 16(b), the efficiency of the proposed ac/ac converter with voltage regulation is shown. The converter maintains the high-efficiency characteristic over the wide gain. The input voltage was varied from 176 V rms to 265 V rms at full load. The peak efficiency of 97.34% was measured at V in = 260 V rms . The minimum efficiency of 96.02% occurs at the minimum operated input voltage of 176 V rms . At input voltage of 176 V rms , the input current is 5.71 A rms which is the maximum rated current. Due to higher conduction losses with lower input voltage, the efficiency of the converter is lower at lower input voltage. The proposed converter also has relatively flat efficiency for wide input voltages.
The DMAC is compared with some recently published work of similar power levels in Table III. The efficiency of the DMAC is found to be higher than the topologies presented in Table III, as also shown in Fig. 16(a) over a wide load range. In Fig. 16(a), the efficiency data is normalized over the reported peak output power to present efficiency comparison in term of percentage output power. As discussed in the introduction, the Type A ac/ac converter performs better in terms of efficiency due to lower conversion stages. The LLC and bidirectional flyback-based Type A ac/ac converter presented in [14] and [32], respectively, also offers high efficiency, however, the presence of folding and unfolding circuit results in a higher number of switches, as noted in Table III. The symmetric half-bridge converter (SHBC) and symmetric full-bridge converter (SFBC) based Type D ac/ac converter presented in [31] and [11], respectively, integrated the DAB converter with the rectifier and inverter stage to reduce the component counts. However, the multiconversion stage suffers from higher losses resulting in lower efficiency. The NIBB-DM with continuous module operation introduced in [21] offered peak efficiency of 93.8%. The low efficiency of the converter can be attributed to the continous operation of the two modules resulting in high conduction losses. In addtion, the hard-switch operation of the switches results in higher switching losses. The DMAC converter, unlike traditional LFT, has the ability to regulate the output voltage with wide input voltage variation. The peak efficiency of the DMAC is >97%, which is comparable to LFT [1]. Fig. 17 presents the estimated loss distribution of the DMAC prototype at full load condition. More than 60% of the losses are incurred through the magnetic components. Design optimization of the magnetic component could further enhance the efficiency of the DMAC. Integration of the input and output inductors [24], [33], [34], [35] on a single magnetic core could also help in reducing the magnetic losses and component counts. The total loss incurred by the clamp circuit switches (S 2 , S 4 , S 6 , and S 8 ) is near 1% of the total loss of the converter grouped under others in Fig. 17.

VI. CONCLUSION
This article introduces an isolated ac/ac converter based on differential-mode architecture. The DMAC is made of two symmetric PWM PAC-Ćuk dc/dc modules connected differentially to enable ac/ac converter operation. The modulation scheme of the modules of the DMAC is discussed in the article to achieve high-efficiency operation. As the dc/dc modules in the DMAC architecture are subjected to time-varying 50/60 Hz sinusoidal input voltages, the converter is required to propagate the low frequency voltage signal to the output port. Hence, the design process and operation analysis of the PAC-Ćuk dc/dc modules in the DMAC application becomes critical and is discussed in this article. A 1-kW hardware prototype was built using the design process outlined in the paper to validate the DMAC. The designed hardware prototype achieved a peak efficiency of 97.28% while maintaining a flat efficiency profile for wide load variation while output voltage THD below 2.18% is also maintained. Similar to magnetizing current in a conventional transformer, the Type A ac/ac converter exhibits capacitative current to build the output voltage. The DMAC results in >0.99 input power factor for a full load operation, however, the power factor degrades with the lower output load as the share of capacitative current to maintain the output voltage increases. The converter is also tested for wide gain by varying the input voltage from 176 V rms to 265 V rms while maintaining the nominal output voltage of 220 V rms . Higher efficiency is observed for lower gain due to reduced copper losses for the same output power. One of the main features of the proposed converter architecture is the modular flexibility and scalability of the architecture. As the DMAC application in power systems requires high power and high voltage rated converters, cascaded, and parallel connection of the modules for the high voltage rating will be explored in the future.

APPENDIX A TRANSFORMER TURN RATIO, n
The transformer turn ratio is dependent on the nominal input and output voltages as given by (27). Equal nominal input and output voltage is considered for the designed hardware prototype of the DMAC resulting in unity transformer turn ratio. In Table IV, the scaling of the output side components of the DMAC for a nominal voltage gain k = V o V in = 1 n is provided.

APPENDIX B ACRONYMS AND SYMBOLS
Some of the common acronyms and symbols used are delineated as follows. LFT Low frequency transformer. DPC Direct power conversion. PAC-Ćuk PWM active clampĆuk. C t1 , C t2 Primary and secondary side blocking auxiliary capacitors. C b1 , C b2 Primary and secondary side blocking capacitors. n Transformer turn ratio. C b Equivalent blocking capacitor referred to primary side C b = C b1 ||n 2 C b2 . L r Inductor in series with C b1 . L in , L o Input and output inductors.
Switches of the Module A. Instantaneous voltage across the equivalent blocking capacitor C bA of Module A referent to primary side of the transformer. v 1 (t), v 2 (t) Instantaneous node voltage across the switch S 1 and S 3 . i 1 (t), i 2 (t) Total current going into the node voltage v 1 (t) and v 2 (t) total current going out of the node voltage v 2 (t).

DISCLAIMER
This article is covered by the following intellectual property: S. K. Mazumder, "Solid-state power-conversion system", US Non-Provisional (Utility) Application No. 17/134178 and International PCT Application PCT/US20/67047, filed on December 2020. (Provisional patent application submitted in December 2019).