GaN-Based Isolated Resonant Converter as a Backup Power Supply in Automotive Subnets

This article presents the analysis, design, and implementation of a 2 MHz, 12 V, 600 mA, GaN-based active-clamped isolated SEPIC converter (ACISC) supporting full zero-voltage switching (ZVS) throughout the 9–18 V automotive range, and intended to provide isolation and power interface between the 12 V battery and the low-power subnet. Designed for resonant discontinuous conduction mode (DCM) operation and leveraging the high switching frequency enabled by Gallium Nitride (GaN) devices, the selected topology leads to a reduction in total magnetic size and footprint, while maintaining a high efficiency profile. Both the theoretical models specifically developed for full ZVS resonant DCM operation, as well as the design and implementation of the transformer, are discussed. The analysis was verified through simulations and experimental measurements taken on a 7.2 W GaN-based prototype employing a planar transformer. Performance comparison with both a 7.2 W GaN-based active-clamped isolated flyback converter (ACIFC) and a commercial flyback converter is also included.


I. INTRODUCTION
I N THE automotive architecture shown in Fig. 1, a variety of low-power electronic loads, such as sensors, microcontrollers, and communication transceivers, are supplied by the 48 V main battery through an intermediate 12 V bus [2]. In case of failure of the latter, the system is sustained by a 12 V backup battery. The isolated converter interfacing the backup battery with the low-power 12 V intermediate bus must operate efficiently over the wide 9-18 V automotive input voltage range, while keeping magnetic size and overall footprint at a minimum. Presently adopted solutions at the industry level are based on Manuscript  the flyback topology with Silicon devices, a poorly efficient solution mostly justified by its low component count and reduced footprint. In this article, a 2 MHz GaN-based active-clamped isolated SEPIC converter (ACISC) [1], [3] is considered a viable substitute for the battery-connected application. In particular, the ACISC topology is here operated in resonant DCM operation to achieve soft rectifier diode turn OFF, i.e., with low di/dt, while ensuring full ZVS of the switches throughout the operating range. While the ACISC topology has been the subject of a number of studies [4], [5], [6], [7], [8], [9], [10], [11], along with similar topologies such as the active-clamped isolated flyback converter (ACIFC) [12], [13], [14], [15], and the asymmetrical half-bridge flyback converter (AHBFC) [16], [17], [18], [19], [20], [21], its design and operation in resonant DCM are still unexplored. For this reason, the contribution of this article is to provide a design methodology to operate the ACISC in resonant DCM while focusing on high-frequency low-power automotive applications. Although here it is considered a battery-connected scenario, the ACISC topology (e.g., operating in resonant DCM operation) can also be used to generate the isolated gate driver power supply for MOSFETs (V out ∼ 15 V). The rest of this article is organized as follows. Section II introduces the topology and its operation in resonant DCM while explaining the advantages of this operating mode. In Section III the analytical expression of the voltage gain M , necessary to develop the theoretical model of the converter, is derived. Section IV addresses the design methodology for the ACISC in order to guarantee full ZVS for both switches over the entire input  voltage variation, along with the design and implementation of the planar transformer. Section V introduces the ACIFC focusing on the differences between the two resonant topologies. Section VI reports the experimental measurements taken on the two 12 V, 600 mA GaN-based prototypes running at 2 MHz and a 400 kHz commercial flyback converter. In this section, both the efficiency profile of the converters and an analytical estimate of the main power losses are provided, together with a comparison in terms of conducted electromagnetic interference (EMI), devices' stresses, physical volume of main components, and thermal analysis as well. Finally, section VII concludes this article.

II. RESONANT DCM OPERATION OF THE ACISC
The ACISC topology originates from the integration of a boost stage with an asymmetrical half-bridge flyback converter (AHBFC) [16], [17], [18], [19], [20], [21], sharing the same switches. Fig. 2 reports the schematic diagram of the ACISC employing two enhancement-mode GaN devices. Converter magnetics consist of input inductor L g and a high-frequency transformer T . In the following, the latter will be modeled by an equivalent primary-side leakage inductance L pe , an equivalent primary-side magnetizing inductance L me , and an equivalent turns ratio n e . Elements C s , C c , and C are the clamping capacitor, the resonant capacitor, and the output filter capacitor, respectively. In the following, small-ripple approximation is assumed for both the clamp and output capacitor, but not for the resonant one. The selected topology features galvanic isolation, low input current ripple, reduced voltage stresses, and full ZVS operation for both switches. Combined with the use of GaN technology, the above features make the ACISC an attractive topology for significantly increasing both the efficiency and the switching rate. Assuming steady-state operation and indicating average quantities with uppercase symbols, the following equations can be derived:  where D is the duty cycle of the low-side switch Q 1 . Fig. 3 shows the main converter waveforms in one of the possible resonant DCM operations. Here, DCM is defined by the output diode D r being OFF during a fraction of subinterval Fig. 3). The ACISC subtopologies which appear during the three different subintervals are shown in Fig. 4. The converter analysis, reported hereafter, makes use of the following parameters: With these preliminary definitions, operation of the converter in the various subintervals can be summarized as follows.
1) Interval 0 ≤ t ≤ DT s [see Fig. 4(a)] At t = 0, the main switch Q 1 is turned ON, while diode D r is already OFF. Thus, the two currents i r (t) and i m (t) increase, in a resonant manner, under the effect of the total voltage v c (t) applied to them. As can be seen in Fig. 3, the currents increase almost linearly since the condition ω ro T s 2π is verified. At the same time, the input current i g (t) linearly increases with a slope equal to Fig. 4 After the commutation of the two switches (turn-OFF of Q 1 followed by the turn-ON of Q 2 ), if the condition is verified, the output diode D r is immediately turned ON, starting the energy transfer phase toward the output. The magnetizing current i m (t) decreases linearly, since the voltage across L me is equal to −n e V o , while C c and L pe continue to resonate. In this subinterval, where Q 2  with t i (i = 1, 2, 3) representing the beginning of each subinterval (t 1 = 0). Expressions of V x , Z o , and ω o , which depend on the considered subinterval, are reported in Table I. Fig. 5 shows the trend of i g (t), i r (t), and i m (t) with their slopes when the ACISC is operated under three operating modes: continuous conduction mode (CCM), resonant CCM, and resonant DCM (highlighted areas mean that D r is OFF). Looking at the first two operating modes, output diode D r is ON either when Q 2 is ON (after t = DT s ) and until i r (t) equals i m (t) at t = D f T s . The reasons why the ACISC is here operated in resonant DCM rather than CCM or resonant CCM operation are mentioned as follows.
1) As shown in Fig. 5, when the ACISC is operated in resonant DCM the output diode D r is turned-OFF with low di/dt, avoiding steep turn-OFF fronts and, more importantly, additional resonances. The last aspect is crucial in this work because, as it will be proved later, the resonant current waveform i r (t) is already affected by resonances generated by making use of interleaved planar magnetics operated in the MHz range. 2) No need for a precise transformer leakage inductance value, since the resonant operation can always be ensured by adjusting the value of the resonant capacitor C c . In other words, for a given value of L pe it is always possible to operate the converter in resonant DCM by changing the value of C c giving rise to subinterval D 3 T s . This is a big advantage because, in the realization of planar transformers, it is difficult to have a strong control over L pe as it happens with L me . 3) Considering the currents available at the switching node at the switching instant and looking at the ACISC resonant DCM waveforms shown in Fig. 5, the ZVS transition for Q 1 and Q 2 depends on both the input current i g (t) and the resonant current i r (t). The latter, which is equal to i m (t) during both transitions, can be easily estimated analytically at t = DT s and t = T s since an approximated triangular waveform can be assumed for i m (t). On the other hand, CCM and resonant CCM call for a precise estimation of L pe to correctly estimate i r (T s ) since i r (T s ) = i m (T s ).
In addition, the estimation of i r (T s ) in resonant CCM is further complicated by its nonlinear behavior. To achieve the aforementioned benefits given by the DCM operation, the ACISC must be operated in resonant mode. In fact, nonresonant operation forces the converter to always operate in CCM, even for very low output current values [4].

III. VOLTAGE GAIN ANALYSIS
In this section, an approximate analysis is presented to relate the voltage gain M and the duty cycle D in resonant DCM operation. When the value of the resonant capacitance C c is reduced to allow resonant operation, its voltage ripple is significant, and cannot be neglected for a correct analytical study of the converter. An approximated closed loop solution can be found for the particular operating point corresponding at the boundary between CCM and DCM operation, i.e., assuming subinterval D 3 T s = 0 (a similar approach was used in [21] for the AHBFC topology). We are going to demonstrate that the derived voltage gain formula yields values close to the simulated ones even when the converter enters DCM. The reason for such result will be explained in the following. Thus, considering the boundary CCM/DCM operating point, the flux balance on the magnetizing inductance L me yields By defining Equation (5) can be rewritten as The expression of V y , from the first equation in (4), is given by with β ω ro DT s , as in Fig. 3. In order to evaluate V y , suitable expressions for the initial conditions V C1 , V C2 , I r1 , I r2 (shown in Fig. 3) must be found. To this purpose, by exploiting the continuity property of the voltage v c (t), it is possible to find the required expressions Then, by assuming an approximated triangular waveform for the magnetizing current i m (t), it is possible to express I r1 and I r2 as Substituting (10) and (9) into (8) yields where coefficients k 1 , k 2 , and k 3 are and Combining (11) with (7) yields the final expression of the voltage gain .
The above expression, which is the main result of this section, is extensively used in the design procedure described in Section IV. The plot of M as a function of D predicted by (16) is shown in Fig. 6, together with simulated and measured data points, that correspond to the design later disclosed in this article. As we can see, (16) fits reasonably well the resonant DCM behavior of the converter across the operating range of interest because the voltage across the magnetizing inductance L me , during subinterval D 3 T s , is not much lower than the value

IV. DESIGN METHODOLOGY FOR ZVS RESONANT DCM OPERATION
The main specifications dictated by the considered application are reported in Table II. The specified switching frequency was selected to avoid disturbance in the AM band since the low EMI noise is a critical requirement for automotive power supplies. The 100 V, 1.7 A EPC2106 eGaN FET pair [22] is selected to implement the two switches. In this work, we want to turn Q 1 and Q 2 ON with ZVS at t = T s and t = DT s , respectively, to keep the switching losses under an acceptable level. To guarantee ZVS, the net current injected into the switching node must have the correct polarity and value at each switching transition. As can be seen from Fig. 3, the ZVS turn-ON of Q 2 (at t = DT s ) is always guaranteed due to the highest positive value obtained either by i g (t) and i r (t), which brings the switching node voltage v sw (t) to the high-level in a few nanoseconds. On the other hand, the critical ZVS transition is the turn-ON of the low-side switch Q 1 at the end of the period, for which i L (t) must be sufficiently negative.
The proposed design procedure is the following. First, determine the amount of current required for the critical ZVS transition. A simple approach is to impose a design constraint on i L (t)-assumed constant and equal to i L (T s ) during the dead time-in order to guarantee enough negative current for the complete ZVS transition of the switching node during the dead time itself, i.e., where C eq,Q is the charge-equivalent capacitance at the switching node [23], V s the switching node voltage at the switching instant, and t D the dead time. Assuming t D ≈ 15 ns, such current can be estimated from the total output capacitance profile C oss (v ds ) of the two switches [22]. Next, considering λ = 6% as a reasonable starting value for the transformer leakage-to-magnetizing inductance ratio of a high-frequency interleaved planar transformer, the possible design pairs (L g , L me ) compatible with the ZVS constraint are considered, and reported in Fig. 7. In the plot, which assumes an initial choice C c = 48 nF for the resonant capacitance and refers to the nominal operating point V g = 12 V, I o = 0.6 A, the ZVS and the hard-switching regions are illustrated. Furthermore, the overlaid contour lines represent the estimated root mean square (rms) value I L rms of i L (t), a quantity directly related to the total conduction losses of the eGaN pair. Such estimation involves the approximation of i r (t) with i m (t), with the consequent almost triangular wave shapes, yielding I L rms ≈ (I g + I m ) 1 + 1 12 where Δi L = Δi g + Δi m . The peak-to-peak current ripple Δi m and the average value of i m (t) are calculated using (10), while I g and Δi g are obtained as To calculate the average value of the input current an efficiency η = 87% is assumed for the considered operating point. The foregoing equations clearly require the duty cycle value to be recalculated for each design pair (L g , L me ), in order to maintain V o = 12 V throughout the design space. This is accomplished by using the voltage gain model (16) developed in Section III. Fig. 7 serves as a design tool to explore the tradeoff in the selection of L g and L me . On one hand, the design point (L g , L me ) should be selected in proximity of the ZVS/hard switching boundary in order to limit the value of I L rms . Within this basic constraint, the ACISC topology offers a degree of freedom in the relative choice of L g and L me , which translates into different amount of peak-to-peak current ripple on i g (t) and on i m (t). The specific design choice here adopted, L g ≈ 2.7 µH and L me ≈ 1.25 µH, is highlighted in the plot with a disk.
Note that choosing a small value for λ-where the latter is a variable in which only L me is controlled by the designer-comes from the initial target of realizing a transformer with a reduced leakage inductance value (interleaving the turns of the windings) to get a higher value for C c while keeping the ZVS resonant DCM operation in nominal conditions. Increasing the value of the resonant capacitor leads to reducing both its voltage ripple (which is significant in the considered operation mode) and the voltage stress across the output diode D r . However, this choice does not represent the unique design methodology for such an application. For example, the designer can be interested in minimizing the transformer's interwinding capacitance C w -which is a critical parasitic capacitance of the converter in the common mode (CM) noise perspective-leading to a higher value of L pe (and, consequently, of λ) since the interleaving between windings no longer represents the correct solution [24], [25]. In any case, one of the main advantages of the resonant operation is to add an additional degree of freedom, since the considered operating mode can always be ensured by adjusting the value of the resonant capacitor C c .

A. Magnetics Design
To obtain the required magnetizing inductance and to reduce the overall footprint, we decided to use a planar transformer based on two ER9.5 half-cores (material 3F4), with a suitable air gap between the central legs in order to obtain the desired magnetizing inductance value. As a first attempt, the selected number of turns is determined starting from an analytical estimate of the core losses P core . Once the peak flux density valuê B is estimated using the following expression: it is possible to calculate P core at a given V g by consulting the P v versusB plot reported in the 3F4's datasheet. The first choice of n 1 = n 2 = 6 turns with 380 µm air gap is determined as an adequate compromise between core and winding losses, the latter being estimated based on the calculated dc windings resistance. Fig. 8 illustrates the planar transformer structure. Each sixturn winding consists of three series-connected layers of two turns each. Each two-turn layer is hosted on a 440 µm-thick PCB module, with one turn on the top and the other turn on the bottom. Primary and secondary layers are interleaved in order to minimize the leakage inductance, and separated by 60 µm-thick insulator sheets. The footprint area of the resulting structure is approximately 245 mm 2 .
As anticipated, in this study the traditional 4-parameters transformer model, accounting for primary-side and secondary-side leakage inductances L p and L s , primary-side  Table III, from which λ ≈ 6.3% is obtained, in good agreement with the design assumption made to obtain the plot shown in Fig. 7.
As far as the required 2.7 µH input inductance is concerned, a six-turn inductor employing ER9.5 cores (same 3F4 material) is realized, measuring the value, at f s = 2 MHz, reported in Table III.  9. Schematic of the GaN-based active-clamped isolated flyback converter, highlighting the adopted model for the high-frequency transformer.

V. REVIEW OF THE RESONANT ACTIVE-CLAMPED ISOLATED FLYBACK CONVERTER
An isolated alternative topology to the standard flyback converter and its viable substitute shown throughout this article is the ACIFC [12], [13], [14], [15]. Fig. 9 reports the schematic diagram of the topology which employs two enhancementmode GaN devices and highlights the adopted model for the high-frequency transformer. Unlike the ACISC topology, this converter exhibits a high-frequency transformer T only as magnetics. Elements C s and C are the clamping capacitor (in this case it also represents the resonant capacitor) and the output filter capacitor, respectively. Although this topology is capable of achieving ZVS for both switches, it does not employ the input inductor L g which results in a higher DM conducted noise compared to the ACISC. On the other hand, the advantage of not hosting L g is that the overall footprint of the ACIFC can be significantly reduced. Another drawback is the higher voltage stress across the switches due to a small value of C s selected to guarantee a resonant DCM operation. However, one advantage of this topology is the lower voltage stress across the output diode D r since there is no dependence on the significant voltage ripple across the resonant capacitor. Table IV shows the expressions of the voltages and currents involved both in the two active-clamped topologies operating in resonant DCM and in a standard flyback converter operating in CCM operation. Note that the schematic of the flyback is the same as that shown in Fig. 9 replacing the active clamp (Q 2 and C s ) with a passive one. When the ACIFC is operated in resonant DCM, magnetizing and resonant currents i m (t) and i r (t) have a similar trend to that shown in Fig. 3 (when Q 1 is ON now there is no resonance and the currents increase linearly). Expressions of resonant capacitor voltage v s (t) and of resonant current i r (t) are similar to the ones shown in (4) (now the coefficients multiplying the sine have opposite sign). Table V reports the new expressions of V x , which depend on the topology and the considered subinterval, together with the resonant voltage and current equations. Following the procedure shown in Section III, even for the ACIFC topology is possible to find an analytical expression of M when the boundary CCM/DCM operating point is considered. The volt-second balance of the magnetizing inductance L me yields where D is the duty cycle of the low-side switch Q 1 . Note that (23) is equal to (16) once the voltage ripple across the ACISC's resonant capacitor C c is neglected (v c (t) ≈ V c = V g ).

A. ACISC Converter
To validate the design methodology shown in Section IV, a 2 MHz 12 V, 600 mA GaN-based converter is realized. Fig. 10 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.
shows the picture of the experimental prototype with a detail of the 6 : 6 ER9.5 planar transformer. The prototype is built around the EPC9055 development board, which features the selected 100 V, 1.7 A EPC2106 half-bridge pair. The development board, which already hosts a 1 µF clamp capacitor C s , is connected at the switching node with a custom-designed PCB, where the input inductor, resonant capacitor, planar transformer, and output rectifier stage are located. The experimentally characterized values of the passive components are reported in Table III. A 40 V, 2 A Schottky rectifier is selected for D r . Because of the large forward voltage drop of the body diode in GaN devices, both driving dead times for the eGaN pair have been adjusted to reduce the body diode conduction time as much as possible throughout the entire input voltage operating range. Such operation was performed manually, once and for all, in nominal condition by adjusting two on-board trimmers (blue boxes in Fig. 10). Fig. 11 reports the converter experimental waveforms for V o = 12 V and I o = 600 mA, when the input voltage V g assumes the minimum, nominal, and maximum values. Despite the high frequency noise, the resonant current i r (t) exhibits the behavior already shown in Fig. 3, especially for input voltages greater than 9 V where the converter starts operating in DCM operation. Fig. 11 shows that the critical ZVS condition is always satisfied, except for the minimum input voltage, for which the current i L (T s ) is not sufficiently negative to allow v sw (t) to complete the entire transition before the end of the dead time. The fixed dead time for the falling edge of v sw (t) is almost equal to 15 ns and is close to the value chosen to plot Fig. 7.

B. ACIFC Converter
The main specifications dictated by the considered application are reported in Table II. The 100 V, 1.7 A EPC2106 eGaN FET pair [22] is still selected to implement Q 1 and Q 2 . As already mentioned in Section IV, the turn-ON of the low-side switch Q 1 represents the critical ZVS transition for which i L (T s ) must be sufficiently negative. Using (18), where V s is the value of v sw (t) at the end of the period, it is possible to estimate the amount of current required for the critical ZVS transition assuming to have the same dead time set for the ACISC (t D ≈ 15 ns). As can be seen in Fig. 12 -which shows the experimental screenshot of v sw (t) in nominal condition-the value of the latter at t = T s is almost 6 V lower then the one obtained for the ACISC [see Fig. 11(b)]. This result represents an advantage for the ACIFC topology since a lower current |i L (T s )| is sufficient to turn Q 1 ON with zero-voltage. On the other hand, as shown in Table IV, a big disadvantage of this topology is the higher average magnetizing current value I m , which calls for a high magnetizing current ripple (i.e. a reduced L me value) to provide a sufficiently negative value to i L (T s ). This leads to higher conduction losses of the eGaN pair and, more importantly, higher transformer primary winding losses. A resonant capacitor C s = 20 nF was used as a replacement of the one hosted by the EPC9055 development board to still have the resonant DCM operation. Fig. 13 compares the efficiency of the designed 2 MHz ACISC (curve labeled T 1 ) with that of the 2 MHz ACIFC (curve Fig. 11. Experimental screenshot of the input current i g (t) (500 mA/div), the resonant current i r (t) (500 mA/div), and the switching node voltage v sw (t) (10 V/div) at V o = 12 V and I o = 600 mA, when the input voltage V g is equal to (a) 9 V, (b) 12 V, and (c) 18 V. Time scale: 100 ns/div. labeled T 2 ) and a 400 kHz commercial flyback converter operating in CCM intended for the same application and having the same input/output voltage and rated current specifications (the measured parameters of the realized transformers T 1 and T 2 are reported in Table VI). The comparison, carried out as a function of both input voltage V g and output current I o , reveals a peak efficiency of the designed ACISC of 87.22% at V o = 12 V and I o = 600 mA, approximately 7.2% better than the commercial flyback converter despite the fivefold increase in switching frequency. Note that the efficiency profile of the ACIFC is far from that of ACISC mainly due to the low value of    L me required for the ZVS operation which results in a significant increase in transformer primary winding losses P wind 1 .

D. Power Loss Breakdown Analysis
At the nominal operating point, the ACISC topology exhibits a total power loss P loss = V o I o (1/η − 1) ≈ 1055 mW. A power loss breakdown analysis is described here, for the ACISC operating in nominal conditions, with the purpose of identifying the main loss sources and estimate their relative contributions. All the analytical estimates are carried out considering a temperature equal to 100 • C, except for the GaN's conduction losses where their real temperature is derived using a Laserliner ThermoCamera (see the thermal measurement reported at the end of this section). Thus, from the EPC2106 datasheet, their ON-state resistance was estimated as R ds,(on) (50 • C) ≈ 1.18 · R ds,(on) (25 • C) = 65 mΩ. As far as the magnetics are concerned, both core losses P core and winding losses P wind are considered, the latter calculated from the measured ac winding resistances R w1,ac and R w2,ac (for the planar transformer), and R w,ac = 283 mΩ (for the input inductor), all taken at 2 MHz (see Table VI, row labeled T 1 ). The estimation of the output diode conduction losses P diode uses both the threshold voltage V T 0 (T j ) and the dynamic resistance R D (T j ), which are extrapolated from the linear fitting of the i F -v F characteristic of the chosen Schottky rectifier. As for the body diode conduction losses of the switches, these are here neglected in light of the preliminary dead time optimization described above. The result of the power loss breakdown analysis for the ACISC topology employing T 1 is shown in Fig. 14, demonstrating a good agreement with the total measured power losses. The largest contribution is associated with the transformer, and in particular with primary winding losses to be attributed to skin and proximity effects in the MHz range. As a matter of fact, the high ac winding resistance is very difficult to predict, being strongly dependent on the leakage flux distribution inside the core window. This, suggested to re-design the planar transformer with a fewer number of turns.

E. Optimization of the Planar Transformer
A new 4 : 4 ER9.5 planar transformer was built for the ACISC to reduce the winding resistance. At the same time, to limit the core losses, the new 3F46 high-frequency material was selected, whose power loss density at 2 MHz andB = 40 mT, is about 85% less than the 3F4 material. The air gap was adjusted to obtain almost the same magnetizing inductance L me and the measured parameters are reported in Table VI (transformer T 3 ). With the new planar transformer the value of the two ac winding resistances is reduced by almost 100 mΩ. The new measured efficiency is also reported in Fig. 13 (curve labeled T 3 ), showing a further improvement of roughly 1.5%.

F. EMI Analysis, Temperature Considerations, and Comparison of Physical Dimensions
Here, we want to compare the 2 MHz ACISC with the 2 MHz ACIFC and the 400 kHz commercial flyback converter in terms of EMI noise, temperature in the main components, and physical dimensions. Concerning the EMI measurements, the experimental setup consists of the following: 1) the equipment necessary to supply the converters; 2) a LISN placed between the power supply V g and the converter's input; and 3) an EMC Analyzer to measure the noise level. The standard CISPR 25-which defines measurement setups and limits of conducted emissions for automotive devices with low-voltage (LV) sources or loadswas adopted, while Class 5 (Peak detector) was considered for the conducted disturbances' limits. Fig. 15(a)-(c) provides the conducted emission at the input for ACISC, ACIFC, and the commercial flyback, respectively (both the standard noise level and the limits are shown). Test results are obtained when the three converters are operated in nominal conditions without EMI filters and with roughly the same total input capacitance. On the other hand, Fig. 16 shows the same results depicted in Fig. 15 with the aim of highlighting the input CM and differential mode (DM) conducted noise. The ACISC is better than the ACIFC topology in terms of conducted emission mainly due to the presence of the input inductor L g which acts as a filter. Comparing Fig. 15(a) with (b), a reduction of almost 10 dBµV can be observed in the ACISC by looking at the first spectral line. The much higher dv/dt of GaN devices, compared with their Si counterparts, increases conducted-and most likely radiatedemissions, especially in terms of CM noise. Indeed, Fig. 16(a) reveals such dominance of the CM noise in the whole considered frequency range. Test results also show that the frequency spectrum of the two GaN-based prototypes exceeds the CISPR 25 limits in the high-frequency range: the use of EMI filters, a better layout, and the optimization of the magnetics in terms of parasitics minimization can help to bring the high-frequency spectral lines under the required limits. Note that the increased ground noise level in the low-frequency range highlighted in Fig. 15(a) and (b), compared with Fig. 15(c), was caused by the external waveform generator used to drive the two GaN switches. Finally, the reason why the bottom part of Fig. 15(b) and Fig. 16(b) (ACIFC results) seems to be cut is due to a selected attenuation value in the EMC Analyzer different from 0 dB.
The thermal images shown in Fig. 17, taken after 20 min of nominal operating conditions (V g = V o = 12 V and I o = 600 mA), reveal almost 27 • C less in the eGaN switches and 8 • C less in the transformer comparing the ACISC with the corresponding components in the commercial flyback. Even if it is not shown in the figures, the overall temperature in the main components hosted by the ACISC is almost 15 • C lower then the one observed in the ACIFC topology due to a lower rms current flowing in the transformer primary winding and switches.
Table VII summarizes the main experimental results obtained for the three topologies in nominal operating conditions. Looking at the results obtained for the GaN-based topologies, the ACISC is better than the ACIFC in terms of efficiency  VII  MAIN RESULTS OBTAINED FOR THE THREE INVESTIGATED TOPOLOGIES (+10%), overall temperature in the main components (−15 • C) and EMI. Physical dimensions are also included in Table VII, where it can be seen that the main components employed in the GaN-based topologies are significantly smaller than those used in the commercial flyback converter.

VII. CONCLUSION
This article addresses the analysis, design, and experimental verification of a 2 MHz, 12 V, 600 mA GaN-based ACISC operating in resonant DCM and intended for low-power automotive applications. The chosen converter operating mode, coupled with the proposed design methodology and high switching rate, guarantees ZVS throughout the intended operating range and leads to reduced magnetic size and overall footprint. A design procedure for the converter is first proposed which enables the designer to tradeoff the input inductance L g and the magnetizing inductance L me while minimizing the total switch conduction losses. The design details for the high-frequency transformer, realized here as a planar structure, and input inductance, are then outlined. Performance comparison in terms of efficiency, temperature in the main components, EMI, devices' stresses, and physical dimensions is carried out between a 2 MHz GaN-based ACISC topology, a 2 MHz GaN-based ACIFC, and a 400 kHz commercial flyback. Experimental results confirm full ZVS operation in nominal conditions of the GaN-based topologies operated in resonant DCM and a better performance from the ACISC topology. Peak efficiency of the optimized ACISC operating in nominal condition at full load is almost 89%, approximately 9% higher than the efficiency of a commercial 400 kHz flyback converter designed for the same input/output voltages and output current rating.