Design Procedure for Reduced Filter Size in a Buck Converter Using a Fourth-Order Resonance Filter

This article presents a novel design procedure for fourth order and fourth-order resonance (4thRes) output filters, for given buck converter specifications, making components selection a straightforward process. An accurate filter analysis is provided to predict the filter component currents and voltages in both frequency and time domains. Application of the analysis in a design study of a 20 MHz, 5.4 W buck converter shows that the 4thRes filter has the potential to reduce the output passive components for a wide duty cycle range. As compared with a second-order filter at VIN = 6.6 V to VOUT = 1.8 V, total inductance, inductor energy, capacitance, and capacitor energy are 58%, 35%, 45%, and 31% lower, respectively. Air-core printed circuit board (PCB) integrated solenoid inductors are considered for implementation and testing within a prototype converter to show the impact of these filters on the converter performance. The 4thRes filter achieved 3.7% and 3.6% higher full-load efficiency than the second- and fourth-order filters, respectively, and a better load transient performance.

voltage ripple [4]. A fourth-order filter, as shown in Fig. 1(b), provides twice the roll-off rate of a second-order filter [see Fig. 1(a)] and, therefore, has the potential for size reduction of the filter components to provide the same level of output voltage ripple.
While various benefits of high-order filters have been reported in the literature, methods for filter design to achieve given dc-dc converter specifications within a minimum size have not been described. Furthermore, the performance of coupled inductors in high-order filters has the potential for significantly reducing the filter size due to the high attenuation they produce through resonance with one of the filter capacitors. However, this has not been fully exploited, partly because there is no detailed analysis available to enable the selection of suitable filter components. These gaps are addressed in this article.
A design procedure for a fourth-order low-pass filter for a dc-dc converter was introduced in [5]. The design procedure focused on increasing the converter bandwidth over a second-order filter (for an accelerator application) rather than on the size of the filter's passive components, where Butterworth, Bessel, and critically damped filters were considered. The first inductance of the filter (L 1 ) was designed based on the inductor current ripple. Then, a normalized filter transfer function was applied to determine the remaining filter components needed to achieve the required attenuation at the switching frequency.
In [6], the focus of filter design for a 100 W, two-phase buck converter was on optimising an envelope tracking system to pass the envelope frequencies of 1.5 MHz and reject the 10 MHz switching harmonic frequencies rather than on minimization of the passive component sizes. After reviewing the filtering performance for a number of fourth-order filters, including Butterworth and Bessel, a Legendre-Papoulis was selected.
A fully integrated 450 MHz buck converter with a fourth-order filter was demonstrated in [7] to have a similar area to a secondorder filter of 0.4 mm 2 ; it was implemented with two side-byside on-chip spiral air-core inductors. It was found that negative coupling (−0.05) due to the placement of the two inductors side-by-side provided greater attenuation than noncoupled at the switching frequency. This is a result of resonance between the mutual inductance and the first stage capacitor, as would be produced between L 3 and C 1 in the fourth-order resonance (4thRes) circuit of Fig. 1(c). However, neither the filter design nor the coupling factor was optimized to target given converter specifications.
A study in [8] investigated the coupled inductor as a filtering block for different applications. A fourth-order filter with a coupled inductor was implemented and tested in a 50 kHz buck converter which showed 22 dB extra attenuation of the output ripple compared with a second-order filter. However, a size comparison was not presented, and the procedure for selecting filter components to achieve given dc-dc converter specifications was not described.
More studies considered high-order filters in different circuit topologies and applications. A 42 kHz, 4 kW 4-phase buck converter with a fourth-order filter, and damping branch in each phase for a magnet power supply in a linear accelerator was described in [9]. A 500 W, 50 kHz buck converter with a fourth-order filter was presented in [10], which utilized the two filter stages to implement two feedback loops for fast envelope tracking. Most recently, a 0.21 W, 118 MHz integrated boost converter with an additional LC stage was presented in [11] to reduce the output ripple for analog applications. However, these studies do not focus on the impact of high-order filters on the size of the passive components.
Therefore, this study provides a novel selection procedure for the passive components in fourth-order and 4thRes output filters with a view to reducing their size for a given buck converter specifications. The performance and size of the resulting filter components are benchmarked against those in a common second-order filter.
As mentioned, with a fourth-order filter, there is an opportunity to implement the third inductor, L 3 , as the mutual inductance between L 1 and L 2 . In this case, analysis of the proposed 4thRes filter using a noncoupled inductor is the first step toward component selection; then a coupled inductor can be used to achieve the same resonance feature. For simplicity, a Butterworth filter is chosen as a starting point for the filter design approach in this article, but other standard filters could be applied.
The comparison is demonstrated for air-core printed circuit board (PCB) integrated inductors, where the target application is the first stage of a 2-stage step-down solution for integrated voltage regulator (IVR) type loads powered by a wide input voltage battery source, e.g., as in [12], where stages 1 and 2 step down battery voltage from 3.8 to 1.5 V and then from 1.5 to 1 V, respectively. This article is an extension of our previous conference paper [13], where new s-domain and time-domain analyzes are presented to predict the voltages and currents in the filter components. In addition, results of experimental testing of the fabricated inductors with a buck converter are included. Section II presents the filter design procedure for a standard fourth-order low-pass filter in terms of the specifications for a dc-dc buck converter. Then, the same approach is applied to the 4thRes filter. Section III provides methods for accurately predicting the voltages and currents of the filter components in the frequency and time domains so that they can be applied in passive component design. The filter design approach is employed to select passive components for a typical step-down buck converter specification, and these are compared against equivalent standard second-order low-pass filter components in Section IV. Implementation of the required inductor designs in PCB is described in Section V, and prototype inductor designs are compared for equivalent second order, fourth order, and 4thRes filters. Prototype converter testing and simulation results are presented and discussed in Section VI. Finally, Section VII concludes this article.

A. Fourth-Order Low-Pass Filter
To analyze the filter components, the following transfer function is derived by circuit analysis of a fourth-order filter, as shown in Fig. 1 where v sw is the switching voltage, v out is the output voltage, R is the load resistance, and L 1 , L 2 , C 1 , and C 2 are the filter's inductive and capacitive elements shown in Fig. 1(b). The transfer function in (1) is compared with the fourth-order normalized filter transfer function, e.g., Butterworth filter where a 1 , a 2 , a 3 , and a 4 are the normalized filter parameters, i.e., 2.613, 3.414, 2.613, and 1, respectively, for a Butterworth filter [14], A n = a n / ω 0 n is used in (3) for simplicity, and ω 0 is the cut-off frequency.
By solving (1) and (3) together, we can get the four filter unknowns L 1 , L 2 , C 1 , and C 2 in terms of the load resistor, R ω 0 is chosen to achieve the required attenuation of the output voltage steady-state peak-to-peak ripple ΔV OUT at the switching frequency ω SW = 2πF SW . ΔV OUT is specified at 5% for the first stage of a 2-stage regulator, where tighter regulation is provided by the second stage on-chip. Note also that in practice, additional output capacitance may be required to satisfy load transient requirements [15], over and abovementioned steadystate ripple filtering, but this is not considered at the initial design phase, where the objective is to assess the switching ripple filtering performances of the various filters. The effect of additional output capacitance for transient requirements is considered in the measurements in Section VI.
As an approximation, ω 0 is calculated assuming the gain of the highest order of the filter transfer function in (3) for each nth harmonic as lower orders are negligible at frequencies > ω 0 , i.e., By assuming that ΔV OUT of the filter is the summation of each harmonic amplitude multiplied by the filter gain at the corresponding frequency, then ΔV OUT is represented as where N h is the number of harmonics required to be attenuated, considering the first 10 harmonics is accurate enough for this study, and ΔV n is the peak-to-peak amplitude of the nth harmonic, which is calculated using Fourier analysis as follows: where D is the switching duty cycle. By substituting (5) and (7) into (6), ΔV OUT is found as As ΔV OUT is a predetermined converter specification, then (8) is solved for ω 0 as follows: In this way, the filter attenuates the switching harmonics to the desired ΔV OUT value at the output signal. This filter design approach for dc-dc converter always results in L 1 > L 2 and

B. 4thRes Low-Pass Filter
In the proposed 4thRes filter [shown in Fig. 1(c)], the inductor L 3 resonates with the capacitor C 1 . Its transfer function was derived using circuit analysis and is simplified to where The resonance of C 1 with L 3 makes a double zero in the transfer function, which is placed at the switching frequency to attenuate the first harmonic amplitude effectively. For frequencies below the double zero, the resonance filter response follows a fourth-order characteristic, and afterwards, it follows a second-order characteristic, which makes the gain at the second harmonic greater than the first harmonic. This will be considered in the selection of the cut-off frequency. The double zero is added to the normalized filter transfer function as follows: By comparing (10) and (12), we can get from the denominator four equations with five unknowns, i.e., L 1 , L 2 , L 3 , C 1 , and C 2 . One unknown is eliminated with the help of the numerator by placing the double zero at the switching frequency to give Substituting (13) into (11) eliminates L 3 , then (11) and the denominator of (12) are solved together to get Similar to Section II-A, ω 0 calculations assume the gain of the highest order of the filter transfer function in (12) for nth harmonic as follows: As (6) and (7) apply here as well, then (7) and (18) are substituted into (6) to express ΔV OUT as follows: Then, (19) is solved for ω 0 as follows: The formulas (13)- (17) are used to determine the component values of the 4thRes filter in a buck converter. This filter design approach always results in L 1 > L 2 > L 3 and C 1 > C 2 . Fig. 2 shows a comparison between the calculated cut-off frequency in (9) and (20) at ΔV OUT /V OUT = 0.05, assuming the first stage specification of a 2-stage converter as discussed earlier. It shows that ω 0 is higher for the 4thRes filter over the whole duty cycle range, which means it is expected to require smaller passive components than the normal fourth-order filter and allow higher bandwidth of the closed-loop converter. However, closed-loop control is not within the scope of this study.

III. FILTER ANALYSIS
In addition to filter component values, the filter size is determined by the voltages and currents carried by each filter component. To predict these voltages and currents, the output filter is first analyzed in the s-domain, including the components' parasitic elements as detailed in Fig. 3, and the results are then translated to the time domain.

A. S-Domain Analysis
To simplify the filter analysis, its components are grouped in the s-domain impedances Z 1 , Z 2 , Z 3 , and Z tot , which are Then, the filter gain is divided into two stages, G 1 and G 2 for the first and second filter stages, respectively, which are combined to get the overall filter gain G filter as follows: Then, inductor currents i L1 , i L2 , and i L3 are calculated This s-domain analysis can accurately predict the frequency components of the voltages and currents of each element. Furthermore, it is used to predict the time domain waveform, which improves the prediction of each component performance and the steady-state output voltage ripple over different loading conditions.

B. Time-Domain Conversion
Assuming linear characteristics of the filter components, the time-domain calculations are done using the standard amplitudephase Fourier representation where A 0 is the average value, A n and ϕ n are the nth harmonic amplitude and phase, respectively, extracted from the s-domain solution in Section III-A. The number of harmonics N is infinity ideally, but N = 50 was found accurate enough for this study, as increasing N increases the computation time. Hence, the switching node voltage is represented as where V n is the harmonic amplitude, V n = ΔV n /2, presented in (7), and T SW is the switching period where I O is the dc output current. As (36)-(40) are in the time domain, they are used to calculate maximum, minimum, and rms values for each filter component, which allows the design and selection of the components.
v OUT (t) from (37) is used to predict ΔV OUT versus loading and, hence, adjust the filter design if needed.

IV. DESIGN STUDY
The considered converter steady-state specifications for this study are listed in Table I, which are typical of point-of-load converter requirements for an intermediate step-down stage, which then is followed by a second stage with tighter output voltage regulation as shown in [1], [12], and [16] for IVR application. The basic buck converter second-order output filter in Fig. 1(a) is taken as a baseline where the inductance and capacitance are calculated based on inductor current ripple (ΔI L ) and capacitor voltage ripple (ΔV OUT ), respectively For comparison purposes, the total capacitance is fixed for the second and fourth-order filters designs (C 2nd = C 1 + C 2 ), so that the improvement in magnetics can be seen. C 1 and C 2 are chosen at the maximum V IN (as a worst-case) according to the procedure explained in Section II-A. As a result, ΔI L for the second order is set to 36.5%.
To compare the inductors' energy, the calculated currents in the fourth-order and 4thRes filters are approximated, as almost all the current ripple in L 1 flows through C 1 . So, the current ripple in L 2 can be neglected. This is seen in the inductor current waveforms from the converter simulation in Fig. 4, which shows that the current in L 2 is almost dc with negligible ripple. Therefore, the total inductor peak energy is calculated as    Fig. 5(a) shows that the fourth-order filter required less inductance than the second-order filter for duty cycles less than 0.62. Meanwhile, the 4thRes filter achieved smaller inductance than the regular fourth-order filter over almost the whole duty cycle range. It achieved smaller inductance than the second-order filter for duty cycles less than 0.74.
The total inductor peak energy in Fig. 5(b) reflects a similar relative trend. Moreover, the smallest total inductor peak energy is achieved by the 4thRes filter, which is 35.6% lower than the second-order design (at the minimum duty). Note that, practical passive components selection for a converter needs to account for the worst operating condition, i.e., at the minimum duty cycle of 0.27.
The total capacitance comparison in Fig. 5(c) shows that the 4thRes filter achieved smaller steady-state capacitance than other configurations. This shows the potential of the 4thRes filter in reducing the size of passive components, with a straightforward design procedure for component selection based on a normalized filter, i.e., a Butterworth filter.
With the aid of the filter design and analysis in Section II, the filter components chosen for the worst-case duty cycle are compared in Table II, showing the advantages of the 4thRes filter in reducing the passive components. These calculations assume   an ESR value of 5 mΩ for C 1 and C 2 branches to account for the parasitic effect in increasing the output voltage ripple in the real converter.
The commercial capacitors selected from Murata for the initial design are shown in Table III. ESR (at 20 MHz) and ESL values were deduced from the datasheet. The 4thRes filter relies on a resonance branch (L 3 -C 1 ), and C 1 consists of four parallel capacitors, each with an effective capacitance of 9.86 nF and parasitic inductance of 0.238 nH. So, the value of L 3 needs to be corrected to 1.55 nH instead of 2.06 nH to maintain resonance at the switching frequency.
The calculated filter gain in (27) is shown in Fig. 6 for the fourth and 4thRes filters, respectively (considering parasitic elements), at 0.1 and 3 A load. Fig. 6(b) shows the resonance notch at the switching frequency of 20 MHz, which attenuates the first harmonic significantly, hence allowing for output filter reduction. Furthermore, the predicted time-domain waveforms and ΔV OUT performance of the fourth and 4thRes filters are shown in Figs. 7 and 8, respectively, at the maximum V IN of 6.6 V. Attenuation at the resonant frequency can also be seen by comparing v C2 and i L2 waveforms in Figs. 7 and 8, where the ripple frequency in the 4thRes is dominated by the second harmonic at 40 MHz rather than at 20 MHz.
Practically, the choice of C 2 is dominated by specifications for voltage over/undershoot during transient load changes rather than steady-state ripple voltage. This may result in a much larger capacitance value for C 2, as demonstrated in Section VI. However, the procedure outlined here ensures that steady-state specifications are met at least, and any additional transient capacitance would act to reduce the steady-state ripple further.

V. PCB INDUCTOR DESIGN
For the prototype converter design, air-core solenoid designs integrated into a standard 2-layer FR4 PCB are considered to illustrate the relative advantage provided by the circuit topologies for inductors fabricated under the same processing constraints. Therefore, while the inductors are not competitive area-wise with inductors having magnetic cores, they illustrate the potential for relative improvement provided by the fourth-order topologies. The inductor design is based on PCB manufacturing constraints, i.e., the copper thickness is 70 μm, PCB height is 1.6 mm, via diameter is 0.2 mm, minimum copper trace width and spacing is 0.15 mm, the via annular ring is 0.125 mm, and the minimum solder mask width is 0.07 mm. For this study, the conductor widths are calculated based on the standard IPC-2221A [17] for a temperature rise of 50°C for the maximum inductor rms current considering passive cooling. The newer standard IPC-2152 [18] can be considered in future work. With these assumptions and constraints, the minimum via-to-via centre spacing is 0.52 mm, hence, the minimum conductor width is 0.37 mm. The inductance of a PCB solenoid inductor, Fig. 9(a), is calculated approximately as where D Via is the PCB via diameter, W Sol and H Sol are the inductor's overall width and height, W C and T C are the conductor width and thickness, respectively, and S C is the conductors spacing. DC resistance of the solenoid inductor is calculated as where R DC_st , R DC_dia , and R DC_via are dc resistances of top layer straight conductors, bottom layer diagonal conductors,  Photos of the manufactured inductors are presented in Fig. 10, which also shows land footprints for the capacitors listed in Table III. A solenoid design is considered for all inductors except L 3 . Its inductance is 1.55 nH, which is too small for a solenoid configuration in PCB, so it is achieved by a single strip conductor shown in Fig. 10(c).
The inductor sizes are compared in Table IV, showing the potential of the 4thRes filter in reducing total inductor size while adhering to practical manufacturing constraints. Size reduction of the 4thRes filter versus the second order (48%) correlates to some extent with the percentage reduction in the calculated peak energy in Table II (35%), while there is a similar correlation with the standard fourth-order filter (20%) reduction in size versus 17% reduction in peak energy). Differences are due to practical restrictions within a given manufacturing technology. The inductor ac resistance is calculated according to Dowell's analysis [19], similar to [20], R AC,n = F n R DC , where F n is the resistance factor at the n harmonic. Only the switching frequency component (first harmonic) is considered for R AC calculation in this study. Then, the inductor power loss is calculated as follows: The calculated inductor losses of the three output filters are presented in Fig. 11 for the converter specifications listed in Table I. It shows a reduction in full load loss at the cost of light load loss. The ac loss in the 4thRes filter occurs mainly in L 1 (although L 1 and L 3 carry almost the same current ripple) because L 1 is bigger than L 3 ; hence, has a much higher ac resistance of 72.8 versus 7.7 mΩ, as shown in Table IV. Overall, there is a tradeoff between inductor size and light-load losses, while both size and full load losses are improved for the 4thRes. The inductors' L S and R S were measured using an impedance analyser at 20 MHz and shown in Table IV, which correlates with the design. The difference between measured and simulated R S values could be due to the following reasons.
• Measurements at 20 MHz are sensitive to accurate calibration of the impedance analyser, particularly short circuit calibration. • The simulation model used solid vias, but they are drilled in the PCB with 25 μm inner wall copper thickness. • Accurate simulation at 20 MHz is challenging as it requires a much finer mesh size of the copper and the air nearby, which requires significant computational resources. With all output filter components chosen, the overall size of the components is compared in Fig. 9(b), which correlates to some extent with the calculated peak energy in Table II.

VI. PROTOTYPE CONVERTER PERFORMANCE
The performance of the converter is investigated in this section with the PCB inductors of Section V, and a buck converter switching stage based on EPC2040 GaN field effect transistors (FETs) [21] for the high and low sides. The EPC2040 rating is 15 V and 3.4 A, and it has a 745 pC total gate charge, which makes it a suitable device for 20 MHz operation. The switches   [22]. The pulsewidth modulation input signal is generated using the DIGILENT Nexys3 field programmable gate array (FPGA) development board, i.e., Xilinx Spartan-6 LX16 FPGA chip, and the output is fed into a high-frequency dc-dc converter test motherboard, which includes variable resistors for dead-time tuning and output transient capacitors. The FPGA was programmed to generate a 20 MHz signal with the duty cycle adjusted externally. The prototype converter board is shown in Fig. 12.
Details of the output capacitor impedances are given in Table V where parasitic ESR and ESL values were deduced from the datasheet. These values were chosen to enable testing of a range of multi-MHz dc-dc converters under steady-state and transient conditions, including the three converters investigated in this article. Clearly, they are much larger than values chosen to satisfy steady-state ripple voltage in Section IV. However, as is typical in multi-MHz converters, the self-resonant frequency of the larger capacitors selected to satisfy transient conditions may be lower than the switching frequency. Therefore, the smaller capacitors' contribution would be most significant at steady state. The operation of the prototype converter was verified, as shown in the testing waveforms in Fig. 13 with the 4thRes filter.   is much lower than the initial specification of 90 mV for the three filters because the fixed output capacitors (in Table V) are much bigger in value than those chosen in Section IV. The measured ΔV OUT value is the same with the second and fourthorder filters (9.5 mV), and it is slightly smaller with the 4thRes filter (7.9 mV).
2) Converter Efficiency: Open-loop circuit simulation is carried out using LTspice with spice models of EPC2040 switches for the high and low sides and for the output capacitors of Table V. To account for parasitic packaging effects, the simulation model considers inductance and resistance values of 400 pH and 0.2 mΩ, respectively, at each FET terminal. The gate signal dead time is 1.1 ns resulting in low-to-high and high-to-low dead-times of ∼36 and 123 ps, respectively, between the FETs reaching the switching point voltage, i.e., 2.2 V approximately according to the datasheet [21]. The experimental dead-time was tuned to minimize the overshoot and undershoot in the switching voltage. Simulated and measured converter efficiencies versus output power at the nominal V IN of 4.5 V are shown in Fig. 15(a) and (b), respectively. Fig. 15(b) includes a curve fit of the measurement data, similar to the method in [23]. The trends in measured efficiency correlate to a large extent with simulation results. Fig. 15(b) shows that the 4thRes filter has slightly lower efficiency than the fourth-order filter below ∼2.5 W. However, the fitted curves show that the full load (5.4 W) measured efficiency of the 4thRes filter is 3.6% and 3.7% higher than the fourth-and second-order filters, respectively. Overall, the difference between measured and modelled absolute efficiency is likely because of factors not included in the model, such as PCB packaging interconnect impedances and eddy current   effects due to proximity with air-core inductors operating at 20 MHz.

B. Converter Loss Breakdown
The spice simulation loss breakdown at full load of 5.4 W and nominal V IN of 4.5 V in Fig. 16 shows that the reduction in total loss of the 4thRes filter is mainly due to the reduction in inductor dc resistance loss and low side FET switching loss.

C. Open-loop Load Transient Simulation
Spice simulation results of V OUT open-loop instant load transition between 10% to 100% load in Fig. 17 at V IN = 4.5 V shows that the 4thRes filter has a faster settling time during loading and unloading as an advantage of utilising less overall inductance. Future work will consider closed-loop performance for the second order versus 4thRes filters.
These results show the opportunity and potential of the 4thRes filter as it resulted in a significant reduction in the passive components' size and an increase in the full-load efficiency without sacrificing the output ripple, besides having a faster settling time during load transients.

VII. CONCLUSION
This article presents a novel selection procedure for passive components in a buck converter with Butterworth-based fourth order and 4thRes filters. The main motivation is to reduce the size of the output filter, particularly the inductor. Previous studies investigated the resonance effect of the output filter of dc-dc converters provided by coupled inductors; however, a selection method for the filter components in terms of the converter specifications was not provided.
The presented study shows the potential of the 4thRes filter to reduce the size of the passive components over a wide duty cycle range. This is confirmed by PCB solenoid inductor structures based on standard PCB manufacturing process limitations. The outcomes of the design study show the potential of the 4thRes filter compared with a second-order filter. For the same output voltage ripple, it provides a 2.4% increase in inductor efficiency at full load, while requiring much smaller passives, i.e., 58% less inductance, 35% less inductor peak energy reflected in 48% less inductor volume. Besides, the 4thRes requires 45% less steady-state capacitance, which results in a 31% reduction in capacitor energy. The prototype converter with the 4thRes filter achieves 3.7% and 3.6% higher full-load efficiency than the regular second and fourth-order filters, respectively. Moreover, the 4thRes filter simulation shows a faster settling time performance during load transients with the same output capacitance, compared with the second and fourth-order filters. These results show that the 4thRes filter can be a suitable replacement for the regular second-and fourth-order filters in dc-dc converters to achieve smaller passive components, particularly for converters operating at higher load and fixed switching frequency.