Evaluation of Threshold Frequencies for Logic Single-Event Upsets at Bulk FinFET Technology Nodes

With modern integrated circuits (ICs) operating at the gigahertz range of operation, the single-event (SE) cross section of an average logic circuit feeding data into a conventional latch has become comparable to the latch SE cross section. Logic SE cross sections at advanced FinFET technology nodes are analyzed to identify the “Threshold Frequencies” at which the logic SE cross section for a typical logic circuit exceeds that of the latch following it. The Threshold Frequency as a function of particle linear energy transfer, supply voltage, and latch design are analyzed for the 16-, 7-, and 5-nm bulk FinFET technology nodes. Results show that the Threshold Frequency is of the order of hundreds of megahertz at these nodes for all test conditions used in this study. Understanding the Threshold Frequency concept and trends will allow designers to harden circuits efficiently to meet design specifications with a minimum performance penalty.


I. INTRODUCTION
S INGLE-EVENT upsets (SEUs) are generally classified into two categories: 1) latch upsets and 2) logic upsets.Latch upsets occur when the collected charge due to an incident ion is at a node contained within a latch cell.Logic upsets may occur when such charge is collected at a node within a logic circuit.The collected charge at a logic circuit node may result in a transient voltage pulse, termed a single-event transient (SET) pulse.This SET pulse may propagate through the logic circuit and reach an input to a latch.If the SET pulse causes the storage of erroneous data in the latch, then a Yueh Chiang is with the Digital IPs Solution Division, Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu 300-78, Taiwan.
Rita Fung and Shi-Jie Wen are with Cisco Systems Inc., San Jose, CA 95134 USA.
Color versions of one or more figures in this article are available at https://doi.org/10.1109/TNS.2024.3365474.
Digital Object Identifier 10.1109/TNS.2024.3365474logic single-event (SE) upset is said to have occurred [1], [2], [3], [4], [5], [6], [7], [8], [9].Logic SE upsets have become increasingly more significant with the reduction of transistor dimensions on an integrated circuit (IC) and circuit operation in the gigahertz range of frequencies.Latch upsets occur when the latch is in a "hold" operation (storing the data).For a flip-flop (FF) with two latches, one of the latches is in hold mode, while the other is in transparent mode based on the state of the clock signal.For a given latch, since the "hold" operation occurs 50% of the time (assuming a 50% clock duty cycle), a latch will always be in "hold" operation for 50% of the time, irrespective of the clock frequency.Assuming uniform incident particle flux, this yields an equal probability of an upset across frequency for a latch.As a result, latch upsets are independent of the clock frequency.Logic upsets, on the other hand, depend on the clock period, and upset rates increase with frequency [10].With ICs fabricated at advanced technology nodes likely operating in the gigahertz range of frequencies [1], [11], the contribution of logic errors to the overall SE cross section of a sequential circuit may be significant.As a result, the characterization of logic errors has become necessary for circuits operating in the gigahertz range of frequencies.
For ICs fabricated at advanced technology nodes, the SE characterization of logic upsets requires operation at high frequencies during irradiation.Since latch upsets are independent of frequency, SE characterization of latch/FF cells can be done at static conditions or low frequencies.However, SE characterization of logic upsets requires all functions related to the estimation of SE error rates (or SE cross sections) to be ON-chip due to difficulties driving input/output (I/O) pins at the gigahertz range of frequencies.These functions include a high-frequency clock generator, error detection, and error counter along with all communication circuits required to export data off the IC.These requirements significantly increase the design complexity and the associated verification and test effort.As a result, most SE characterization studies usually focus on latch SE cross section and may not account for logic upset contributions to the overall SE cross section.
Experimental results at the 28-nm bulk planar node showed that SE cross section for logic upsets will be comparable to conventional D-FF SE cross section beyond 1 GHz Fig. 1.Frequency dependence of logic error SE cross section for the alpha particles and D-latch error SE cross section at the 28-nm bulk planar node, after [12].
frequency [12], as shown in Fig. 1.At this technology node, a sequential circuit operating at 3 GHz frequency will certainly have logic SE cross sections dominating the overall SE cross section of the sequential circuit.Results from advanced technologies also show similar results at the gigahertz range of frequencies [12], [13], [14], [15], [16], [17] With most application-specific ICs (ASICs) fabricated at advanced FinFET technology nodes operating in the gigahertz range of frequencies, logic upsets have the potential to dominate the overall SE cross section.
For a given design, designers may need to selectively harden cells to meet SE specifications.If the latch upsets dominate the overall SE cross section for the sequential circuit, then designers should prioritize hardening the latches by applying spatial or temporal radiation-hardening by design (RHBD) methodologies [18], [19], [20], [21].On the other hand, if logic upsets dominate the SE cross section for the sequential circuit, then only hardening latch cells may not sufficiently reduce the overall SE cross section and meet design specifications.For such a case, designers may need to harden logic circuits and/or latch circuits to meet design specifications.During the design phase, designers need to identify the most efficient hardening approach by understanding whether latches or logic circuits are the major contributors to SE cross section.
A useful metric for determining the majority contributor to SE cross section is the frequency at which the logic upset SE cross section will be equal to the latch SE cross section, referred to as Threshold Frequency in this work.Threshold Frequency is a function of the technology node, supply voltage, latch cell design, logic cone design, logic cone input voltages, and particle linear energy transfer (LET) [12].Most designers focus on improving the latch upset SE cross section by using RHBD techniques for FF cells.If the circuit is operating above the Threshold Frequency, then hardening FF designs may not yield sufficient reduction in the overall SE cross section of the sequential circuit because the logic upsets will likely dominate the overall SE cross section.In those cases, hardening the logic circuits will be more effective.Knowledge of the Threshold Frequency will allow designers to optimize the application of RHBD techniques for a given technology node and improve the overall performance of a circuit.In this work, logic SE cross sections and Threshold Frequencies are evaluated at the 16, 7, and 5-nm bulk FinFET nodes for heavy ions and alpha particles to demonstrate the Threshold Frequency metric.

II. BACKGROUND
Logic SE cross section is given by # sensitive nodes SET pulse−widths where E is the electrical masking factor, L is the logical masking factor, A is the sensitive area for a given SET pulsewidth for a given logic gate, and T is the temporal masking factor for a given FF design [10], [13], [14], [22].The first summation is over all SET pulse widths generated for a given sensitive node.The second summation is for all sensitive nodes in the given logic circuit.The number of sensitive gates, logical masking, and temporal masking will depend on the design of the sequential circuit.All the factors in (1) are independent of frequency except for the factor T .The factor T , temporal masking factor, is defined as where t SET and t SH are the SET pulse widths and setup-&-hold time, respectively, of a latch during a clock period of t cycle [10].
The clock cycle value in the denominator makes the logic SE cross section an almost linear function of frequency when clock cycles are much longer than SET pulse widths [23], [24], [25].If the SET pulse widths are comparable to the clock cycle, then the SE cross section becomes a sub-linear function of frequency [10].At the advanced bulk FinFET technology nodes, ion strikes may generate SET pulse widths ranging from 10 to 100 ps, depending on the circuit design, operating conditions, and particle LET values [13], [14], [26], [27].For circuit operation up to 1 GHz, the clock period will be at least an order of magnitude longer than SET pulse widths for heavy ions in these technology nodes, yielding an almost linear relationship between logic upset SE cross section and operating frequency.
Assuming that the logic SE cross section is linear with frequency and that the latch SE cross section is independent of frequency, the SE cross section for both types may be depicted as shown in Fig. 2 as a function of frequency [23].The Threshold Frequency, or the frequency at which the latch SE cross section is equal to the logic SE cross section, is dependent on the slope of the logic SE cross section as a function of frequency and latch SE cross section.Factors other than the temporal masking factor also play a role in determining the slope of the logic SE cross section.These factors are the logical masking factor (technology agnostic, but circuit design dependent), electrical masking factor (circuit design and technology dependent), and sensitive area (circuit design and technology dependent).Logic SE cross sections are usually specified per logic gate, i.e., SE cross section for a single Inverter, NAND, or NOR gate.The overall logic SE cross section for a circuit is calculated by multiplying an average value for the logic gate SE cross section with the  number of sensitive gates in the logic circuit associated with each latch.Since the number of sensitive gates per logic circuit will vary across an IC (which will vary the slope of logic SE cross section), an average number of sensitive logic gates per logic cone is used in this study.It is assumed that there will be an average of eight sensitive logic gates for any logic cone feeding data into a latch for an ASIC, with the number of logic gates in a logic cone ranging from 25 to 30 gates.
When a latch/FF cell is hardened, the curve shown in Fig. 2 changes to the one shown in Fig. 3.The hardened latch SE cross section value decreases, but the logic SE cross section curve may remain unaffected (if the setup-&hold time of the hardened latch is similar to that of the original latch).If the circuit was operating at a frequency above the Threshold Frequency, the logic SE cross section would still dominate, and the latch hardening may not result in a sufficient reduction in the overall SE cross section to meet the application requirements.In such a case, designers will need to harden logic circuits to reduce the slope of the logic SE cross section curve and the overall SE cross section for the circuit.The slope of the logic SE cross section is a function of technology node, logic circuit design, particle LET, and supply voltage (all these factors affect SET pulse-widths in (1)) [12], [13], [14].Fig. 4 depicts an increase in Threshold Frequency when the slope of the SE cross section curve is reduced (a shift down in log-log scale).The overall SE cross section for the sequential circuit also decreases.The changes to the total SE cross section in Figs. 3 and 4 illustrate that operation at frequencies significantly higher than the Threshold Frequency will require designers to consider hardening logic circuits along with latch circuits to meet design specifications.
Generally, it has been assumed that logic SE cross section and latch SE cross section will decrease with scaling for a given sequential circuit (comprising logic and latch cells).Whether the changes with scaling will result in an increase or decrease in the Threshold Frequency is decided by the latch SE cross section as well as the slope of the logic SE cross section at each node and design.Figs. 3 and 4 can be used to observe the cases in which Threshold Frequency could decrease or increase depending on the relative changes to the logic and latch cross section slope.Increasing particle LET or decreasing the supply voltage will increase the SET pulse widths, which increases the probability of latching an SET pulse.This will increase both the slope of the logic SE cross section curve and the latch SE cross section.Changes to these variables will also result in changes in the Threshold Frequency, and subsequently shift the overall SE vulnerability of ASICs.
Most latch-hardening techniques impose a performance penalty in terms of area, speed, and power which will degrade the speed and performance of a circuit.RHBD approaches for latch designs also tend to increase the setup-and-hold time.Increasing setup-and-hold time will affect the logic SE cross section, as per (2), so reducing the SE cross section of a latch affects the SE cross section of the associated logic circuit.The fact that both the latch and logic SE cross sections are intertwined means it is important to identify the Threshold Frequency for modeling SE error rates.Designers need to know how the interplay between latch SE cross sections and logic SE cross sections will affect the Threshold Frequency, and subsequently the overall SE cross section for a sequential circuit.The Threshold Frequency metric will account for changes to both latch and logic SE cross section and guide designers on which cells to harden for maximum effectiveness.This work has carried out experimental characterization across multiple technology nodes to determine the Threshold Frequency as a function of particle LET and supply voltage.These results clearly show that hardening techniques must be applied to both latch and logic circuits to reduce SE cross sections to desired levels when ICs are operating in the gigahertz range of frequencies.

III. DESIGN, SIMULATIONS, AND EXPERIMENTAL DETAILS
Custom-designed test ICs were fabricated using commercial 16-, 7-, and 5-nm bulk FinFET technologies.Shift registers with different FF designs were implemented along with ON-chip error detection and error counting circuits [28].Shift registers with 8K and 32K conventional D-FFs were used in this study.The D-FF designs used a medium threshold voltage (V T ) option offered at each technology node.On-chip clock generation allowed for clock frequencies up to several gigahertz for each test IC.All support circuits (such as clock generation, error detection, error counting, etc.) were designed with triple modular redundancy (TMR) to eliminate errors from support circuits.The size of the test die was 2 × 1 mm.
During irradiations, shift registers were clocked at frequencies ranging from 2.5 MHz to 1 GHz.ON-chip error counters were used to enable high-frequency operation.An FPGA (Altera DE2-115) was used to control the test IC and automated scripts were used to tabulate the number of errors that occurred in each shift register of interest.The FPGA was placed away from the beamline to avoid any corruption of data.
Heavy-ion tests were carried out at Lawrence Berkeley National Laboratory (LBNL) using 16 and 10 MeV/n cocktails to cover a wide range of LETs.All tests were done at normal incidence and ambient temperatures.The shift registers were given a constant input of either "1" or "0."During each test, the inputs to the shift registers were held constant to eliminate all errors caused by ion hits on the clock tree.Tests were performed for core supply voltages of 800 mV (nominal for 16-nm), 750 mV (nominal for 7-and 5-nm), 650 mV, and 550 mV.Test results were analyzed to separate latch errors and logic errors [29].Logic errors were further analyzed to calculate the SE cross section for an average of seven sensitive nodes per latch as a function of supply voltage, particle LET, and technology node.
Error bars were calculated using Gaussian standard error corresponding to 1σ .Error bars were smaller than the marker size in most cases.All data has been normalized to allow for comparison between datasets.Logarithmic scales for both latch and logic SE cross section and frequency were used to compare SE cross sections that result in different orders of magnitude.

A. Method for Estimating Logic SE Cross Section for a Typical Logic Circuit Using Experimental Data
Each FF design is composed of a primary latch and a secondary latch.The primary stage latch will accept data during one clock state, such as clock LOW, and hold data during the other clock state, such as clock HIGH.The secondary stage latch operates the same but accepts and holds data on the opposite clock states.For a sequential circuit, when the primary stages are active and accepting data, the sensitive logic gates will include the gates from the secondary stage of the previous FF and any combinational logic between the FFs.When the secondary stages are active, the sensitive logic gates will only be those in the primary stages.For a 50% duty cycle operation, the effective number of sensitive logic gates will be the average of the two cases.Generally, the logic circuit in between FF cells is composed of 25 to 30 logic gates with a logic depth of 6 to 10 gates.Due to logical masking, the average number of sensitive logic gates/nodes for such a circuit may be assumed to be eight.For a conventional D-latch, there are three sensitive nodes in each of the stages (primary and secondary).With the eight sensitive gate logic cone feeding data into the primary latch, these values will yield 11 sensitive nodes when the clock is LOW and three sensitive nodes when the clock is HIGH, resulting in an average of seven sensitive nodes per clock cycle.Multiplying the experimental logic SE cross section per logic node by seven will yield the average logic SE cross section per latch cell.The logic SE cross section presented here is based on minimum-size sensitive nodes from an inverter.Logic gates with different size transistors (or functions, such as NAND or NOR) will yield different SE cross section values due to differences in area, drive currents, and nodal capacitances.Designers can account for these by extrapolating the value of the SE cross section for different logic gate designs.In complex designs that use combinatorial logic feeding into FFs, the logical masking will reduce the logic error sensitivity and result in a lower contribution of the SETs to SEU cross section.The Threshold Frequency exhibits an increase relative to the amount of logical masking from combinatorial logic.It is essential to note that the findings presented in this article can serve as a conservative estimate for the Threshold Frequency, as the analysis is based on data derived from the transparent stage of the FF, without any logical masking applied.

B. Threshold Frequency Trends With Scaling
Fig. 5 shows the logic and latch SE cross sections for the 16-, 7-, and 5-nm bulk FinFET nodes for conventional D-FF design and assuming an average of seven sensitive nodes for Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
the logic circuit.The experimental D-latch SE cross sections are for nominal voltage operation and saturated SE cross section values (high LET particles) for all three nodes.The particle LET is sufficiently high so that the SE cross sections were all saturated: 45 MeV-cm 2 /mg for the 16-nm node, 25 MeV-cm 2 /mg for the 7-nm node, and 35 MeV-cm 2 /mg for the 5-nm node.The latch SE cross sections were obtained using the 2.5 MHz data [29] previously published in [27], [30], and [31].The latch SE cross sections were deducted from the total SE cross sections as a function of frequency to model the logic SE cross sections per the method discussed in Section IV-A.A line is fit to the modeled logic SE cross section to determine the Threshold Frequency.The fit assumed the relationship between SE cross section and frequency was linear and there was no logic SE cross section at 0 MHz.Fig. 5 shows the Threshold Frequency for 16, 7, and 5-nm nodes are approximately 550, 340, and 230 MHz, respectively, which are all lower than the 1.6 GHz Threshold Frequency estimated for the 28-nm bulk planar node [12].It must be emphasized that the 28-nm node evaluated groups of inverter chains (with NOR and inverters) as the logic circuit, while the logic circuit modeled here for the 16-, 7-, and 5-nm nodes is for seven sensitive nodes based on inverters and pass gates.Different sensitive areas for individual logic gate designs (along with other technology-related factors) will affect the slope of the logic SE cross section for each node, and subsequently the Threshold Frequency.
For all three nodes, the Threshold Frequencies are significantly lower than the usual operating frequencies for ASIC designs.Most ASIC designs at these technology nodes operate in the 3 GHz to 7 GHz range.For the 16-, 7-, and 5-nm nodes, the Threshold Frequencies are hundreds of megahertz, indicating that any ASIC operating at a few gigahertz will have SE cross sections dominated by logic upsets.Hardening the latch designs for these circuits will not significantly improve the overall SE performance.
The slope of logic SE cross section as a function of frequency in Fig. 5 shows trends similar to what has been observed for latch SE cross section for these technologies [27].The 7-nm node shows the lowest latch SE cross section among these nodes, and the slope of the logic SE cross section also shows the lowest value for the 7-nm node.The increase in slope for logic SE cross section at the 5-nm node indicates an increased vulnerability to logic upsets at the 5-nm node compared to that for the 7-nm node.The Threshold Frequency decreases with scaling due to the relative changes in logic SE cross section slope and latch SE cross section, resulting from the changes to critical charge (charge required to generate a SET pulse of a given duration) and collected charge with scaling [27].The decrease in Threshold Frequency with scaling indicates that designers will need to be cognizant of logic SE cross sections at advanced technologies.

C. Threshold Frequency Trends With Particle LET, Supply
Voltage, and Latch Design Fig. 6 shows the D-FF SE cross section as a function of frequency for 35 MeV-cm 2 /mg heavy-ions and alpha particles Fig. 6.Logic and latch SE cross sections for the 5-nm bulk FinFET node at nominal supply voltage for alpha particles and heavy ions.Note that the y-axis is on a logarithmic scale to aid comparison.
for the 5-nm node.The SE cross section is shown on a logarithmic scale to aid visual comparison.The slope of the logic SE cross section increased for high-LET heavy ions by two orders of magnitude compared to alpha particles.The latch SE cross section increased by about three orders of magnitude.These increases are caused by an increase in the SET pulse widths.The SET pulse widths produced by heavy ions will be much longer than those for alpha particles.A logic upset will occur when an SET pulse is present during setup-and-hold time of a latch.With longer SET pulse widths for high-LET ions compared to alpha particles, the probability for perturbation of the input voltage to the latch during setup-&-hold times increases.Even though the logic SE cross section for high-LET particles is higher than that for alpha particles, the greater abundance of low-LET particles in radiation environments compared to high-LET particles means the contribution from all particles is important.The Threshold Frequencies for both particles are different due to the resulting changes to both the latch and logic SE cross section as particle LET increased.For alpha particles, the Threshold Frequency is estimated to be about 20 MHz, compared to 230 MHz for the heavy ions.The Threshold Frequency is higher by an order of magnitude for the high-LET particles compared to that of alpha particles since the latch SE cross section increased more than the logic SE cross section slope in this case.It should be noted that the Threshold Frequency is influenced by the design of the logic circuit, and the Threshold Frequencies observed in this study should be understood as representative trends modeled for seven minimum-sized sensitive nodes per latch.Fig. 7 shows the changes in Threshold Frequencies as a function of supply voltage for heavy ions for the 5-nm node.A reduction in supply voltage increases the slope of the logic SE cross section curve, but it also increases the latch SE cross section values.When the supply voltage is reduced from 750 to 550 mV, the slope of the logic SE cross section as a function of frequency and latch SE cross section both increase by about a factor of five.As a result, the Threshold Frequencies are similar between the 750 mV and 550 mV conditions.In contrast, reducing the supply voltage from 750 mV to 650 mV results in a lower Threshold Frequency since the increase in the latch SE cross section is less than the increase in slope for the logic SE cross section.At the 5-nm node, changing supply voltage yields only a small change in Threshold Frequency, and importantly, the trends in Threshold Frequency as a function of supply voltage are not consistent.Because of the interplay between logic and latch SE cross sections with SET pulse widths, designers will need to utilize empirical models to evaluate the effects of various parameters, such as supply voltage, to identify changes in Threshold Frequencies.
A guard-gate (GG) FF was also evaluated at the 5-nm node with alpha particles, as shown in Fig. 8, using the same assumption of an average of seven sensitive logic gates per clock cycle.The GG-FF latch SE cross section and logic SE slope are both 10× lower than that of the D-FF.The decrease in latch SE cross section is expected for the hardened latch design.The decrease in logic SE cross section slope is mainly due to the increased setup-&-hold time requirement of the GG-latch.Due to increased setup-&-hold requirements, the temporal masking factor changes and all SET pulses with pulse widths shorter than a threshold value will not result in an error.The reduction in SET pulses capable of causing an error results in a decreased slope for logic SE cross section.The Threshold Frequency is still similar overall since the reductions in both latch and logic SE cross section are in tandem.These results indicate that Threshold Frequency is a complex function of many parameters and must be established empirically.

V. CONCLUSION
With ASICs fabricated at advanced technologies operating in the gigahertz range of frequencies, logic upsets are expected to dominate over latch upsets.Most designers are focused on hardening latch designs to meet product-level SE performance specifications.Results presented here show that hardening only latches may not result in significant improvements in overall SE performance for sequential circuits.Designers will need to be aware of the contributions of logic SE cross section to the overall SE cross section above certain frequencies.The Threshold Frequency metric presented in this article will allow designers to evaluate their designs quickly and determine the optimum hardening approach to apply to their designs.
In this work, the latch and logic SE cross sections and Threshold Frequencies of 16-, 7-, and 5-nm bulk FinFET technology nodes were compared for different particles and supply voltages using experimental data.Similar to latch SE cross section values, the logic SE cross section showed the best performance for the 7-nm node, while 16 and 5-nm nodes showed comparable logic SE cross section values for heavy ions.The Threshold Frequency was approximately 550, 340, and 230 MHz for the 16-, 7-, and 5-nm bulk FinFET designs evaluated in this study.The Threshold Frequency decreased with scaling due to relative changes in logic SE cross section slope with respect to frequency and the latch SE cross section.The trends and the estimated values of the Threshold Frequency must be taken into consideration by designers to meet IC-level SE specifications.These results also clearly show the limitations of using only latch SE cross sections in modeling the overall IC-level SE vulnerability.

Manuscript received 5
October 2023; revised 1 January 2024; accepted 3 February 2024.Date of publication 13 February 2024; date of current version 16 August 2024.This work was supported in part by the Soft Error Consortium and in part by the U.S. Department of Energy National Nuclear Security Administration for Program support from the Stewardship Graduate Fellowship under Grant DE-NA0003960.(Corresponding author: Yoni Xiong.)Yoni Xiong, Nicholas J. Pieper, Jenna B. Kronenberg, and Bharat L. Bhuva are with the Department of Electrical and Computer Engineering (ECE), Vanderbilt University, Nashville, TN 37235 USA (e-mail: yoni.xiong@vanderbilt.edu).

Fig. 2 .
Fig. 2. Conceptual illustration of the logic and latch components of SE cross section as a function of frequency.Note the log scales.

Fig. 3 .
Fig. 3. Changes to threshold frequency with hardening of latch.Hardening the latch decreases the latch SE cross section and threshold frequency.

Fig. 4 .
Fig. 4.Changes to threshold frequency if logic circuits are hardened.Hardening the logic circuits reduces the slope of the logic SE cross section and increases the threshold frequency.

Fig. 7 .
Fig. 7. Threshold frequencies and 5-nm heavy ion latch and logic SE cross sections as a function of supply voltage for heavy ions.Note that the y-axis is on a logarithmic scale to aid comparison.

Fig. 8 .
Fig.8.Threshold frequencies and 5-nm latch and logic SE cross sections for D-FF and GG-FF after alpha particle exposure at nominal supply voltage (750 mV).Note that the y-axis is on a logarithmic scale to aid comparison.