Design of an 87% Fractional Bandwidth Doherty Power Amplifier Supported by a Simplified Bandwidth Estimation Method

This paper presents a novel technique for the design of broadband Doherty power amplifiers (DPAs), supported by a simplified approach for the initial bandwidth estimation that requires linear simulations only. The equivalent impedance of the Doherty inverter is determined by the value of the output capacitance of the power device, and the Doherty combiner is designed following this initial choice and using a microstrip network. A GaN-based single-input DPA designed adopting this method exhibits, on a state-of-the-art bandwidth of 87% (1.5–3.8 GHz), a measured output power of around 20 W with 6 dB back-off efficiency between 33% and 55%, with a gain higher than 10 dB. System-level measurements prove the linearizability of the designed Doherty amplifier when a modulated signal is applied.


I. INTRODUCTION
T HE Doherty power amplifier (DPA) is widely adopted in mobile base-stations for its ability in amplifying modulated signals with high peak-to-average power ratio (PAPR) while maintaining high efficiency [1], [2].Several licensed bands are assigned to 4G systems, especially in the 1.6-3.5 GHz range, making the design of DPAs able to operate on different bands of great interest for the provision of a single hardware easily configurable to the specific frequency adopted in the small cell.
Unfortunately, DPAs are affected by several bandwidth limiting factors that extend beyond the typical broadband matching problem in combined PAs and, as a consequence, the scientific and industrial communities have spent a considerable effort in investigating techniques for bandwidth improvement in DPAs.Most of the relevant papers on this topic focus their attention on the output combiner.The work in [3] analyzed the impact of the output capacitance in an LDMOS DPA, while the work in [4] focused on the impedance inverter in a GaN DPA, proposing an alternative output combiner for improved bandwidth.A comprehensive analysis of the bandwidth limitations given by the output section of DPAs was discussed in [5], where two prototypes were designed according to a broadband matching achieved following a simplified real frequency technique.Moreno et al. [6] proposed a GaN-based 3-3.6 GHz Doherty that exploited output compensation networks.In [7], the bandwidth of the classical DPA was expanded using a quasi-lumped quarter-wave transmission line and the Klopfenstein taper.A modified output combiner, based on a nonterminated branch line coupler, was proposed in [8], and then has been improved in [9] to achieve a record bandwidth of 83%.In [10], a broadband GaN DPA, operating on the 1.6-2.4-GHzband, has been designed focusing the attention on the auxiliary amplifier output in order to maximize the power utilization of the adopted devices.A "postmatching" architecture was adopted in [11], obtaining a 42% bandwidth in a 40-W GaN-based DPA.The work in [12] showed a sequential PA using a Doherty-type modulation, achieving a 30% bandwidth adopting GaN devices.A very recent contribution [13] has demonstrated a 50% bandwidth DPA adopting a systematic continuous mode approach [14].State-of-the-art bandwidth has been achieved through the use of the so-called "Digital Doherty," where the main and auxiliary inputs are driven with independent modulated signals [15], [16], and proper digital signal conditioning accounts for the output section bandwidth limitations.On the other hand, the utilization of separated baseband processing and up-conversion chains asks for a redefinition of the transmitter: in this case, the pros and cons with respect to standard solutions must be carefully evaluated.This paper presents the design, simulation, and characterization of a GaN-based 20-W single-input DPA, showing a state-of-the-art bandwidth of 2.3 GHz (87% fractional bandwidth), ranging from 1.5 to 3.8 GHz.This paper is organized as follows.Section II describes the proposed new design technique, supported by a novel method for simplified bandwidth estimation in the preliminary assessment of the design.Section III describes the application of the design technique to the specific design, while Section IV describes the translation from ideal components to microstrip and the simulation results.Section V shows the measurements, and finally Section VI draws some conclusions.

A. Bandwidth Estimation
The bandwidth of the DPA could be defined as the frequency range F P on which the saturated output power P OUT,sat is larger than a target P OUT,target .However, in this paper, it is also introduced F L , defined as the frequency range on which the gain compression or expansion in the Doherty region is lower than a target.The DPA bandwidth becomes the intersection F P ∩ F L .The gain compression/expansion can be estimated as the difference between input power back-off (IBO) and output power back-off (OBO), where the back-off is the power range between the Doherty breakpoint and maximum power.This compression figure provides an initial control on the nonlinear distortion focusing on the span of the Doherty region.It has to be recognized that DPA distortion is also affected by other factors, as phase distortion, and in general, it is not limited to the Doherty region only, but it is present at low power due to weak nonlinear effects mainly related to the nature of the active devices [17]- [19].Despite these limitations in accuracy, defining the range F L is useful and convenient, because a first assessment of the difference between IBO and OBO can be achieved through the approach proposed in this paper.
In fact, following these guidelines, a simplified bandwidth estimation can be carried out using the scheme in Fig. 1, where the current sources I M and I A represent the main and auxiliary devices, respectively, and the two-port Z matrix represents the output combiner, including the load.This method allows to monitor F P and F L through the evaluation of Z that can be easily obtained by linear simulations running in real time during the tuning or optimization of the circuit elements.This initial bandwidth estimation does not need to rely on nonlinear simulation that can be used instead in a second phase to refine the design.
Potentially, considering fundamental and harmonics would lead to a more accurate approximation of the performance than considering fundamental only.On the other hand, the detection of clipping when considering harmonics is possible but not without a significant added complexity [20].Moreover, the input harmonic terminations have a strong impact on the effect of output harmonic loads, and in a broadband design, it is very difficult to ensure that input harmonics are shorted or controlled.For these reasons, harmonics are neglected in this simplified analysis.The ac voltage at the device drain terminals can be evaluated as Assuming devices with maximum current I MAX and ρ I MAX for the main and auxiliary devices, respectively, then ( The current ratio factor ρ is used when a different auxiliary device size is chosen; otherwise, it can be set as one.The parameter φ is a frequency-dependent phase delay determined by input splitting and matching, while i 1M , i 1 A are the dimensionless fundamental Fourier components of the current waveform at maximum drive for the main and auxiliary, respectively.For example, in a class B-class B Doherty, both i 1M , i 1 A are equal to 0.5 at each drive level, while in a more typical AB-C configurations, i 1M , i 1 A are drive dependent and in general not identical.The saturated power can be estimated by imposing the device currents at their maximum value.
Ideally, with devices without voltage limitations, this would lead to However, in a more realistic device approximation, in order to avoid top current clipping, it is necessary to maintain the voltage magnitude below V MAX = V DD − V K , where V DD and V K are the drain bias and knee voltage, respectively [21].Since the values of the Z-matrix are fixed, the only way to reduce voltage is by reducing the current that is controlled by the input drive.The effect of drive reduction can be accounted by introducing a current reduction factor σ x , where x represents the main or auxiliary stage Since we consider the main and auxiliary drive as not independent, the effective current reduction factor at each frequency must be chosen as σ = min{σ M , σ A }.The effective current at saturation is while the effective voltage at saturation is Fig. 2 shows an example to clarify the role of σ .At the Doherty breaking point, the auxiliary is turned OFF (I A = 0) and the main fundamental current is reduced by a factor γ that is related to the power back-off with a square law, according to the simplification in [22].For example, for a 6-dB Doherty design, γ = 2.The voltage at the main device is determined as Fig. 2. Graphical interpretation of the current reduction factor σ .
If V M,back > V MAX , another current reduction term β must be adopted to avoid current clipping, being The effective back-off current and voltage result as The output power at saturation and back-off can be calculated, assuming lossless matching networks, as The OBO in decibels is defined as 10 log 10 (P OUT,sat / P OUT,OBO ), while the IBO can be evaluated as 20 log 10 (V in,max /V in,obo ), where V in,max and V in,obo are the drive voltage needed to generate the maximum and the back-off current, respectively.In a B-B Doherty simplification, IBO = 20 log 10 (γ /β).From these results, the frequency ranges F P and F L can be derived according to the matching strategy, i.e., to the calculated Z matrix.Moreover, a very rough estimation of the saturated and back-off efficiency can also be carried out, by evaluating the dc power consumption as The Fourier dc current components i 0M,max , i 0A,max , and i 0M,obo can be calculated according to the conduction angle of the current waveform at effective maximum and back-off conditions.For a B-B simplification, their value is A first estimation of the bandwidth can be applied to guide the design of the Doherty PA by following these steps.1) Choose a Doherty combiner topology.
2) Setup a linear simulation for the Z-parameters of the combiner, including the output equivalent circuit of the devices.3) Use the equations of this section to evaluate the fig- ures of merit (output power, IBO, and OBO) that determine F P and F L .4) Evaluate F P and F L and use them as goals for optimization while tuning the combiner's parameters.After this procedure, the topology can be applied in a full nonlinear simulation for the refining of the Doherty design.

B. Design Strategy
In this section, we present the specific strategy adopted for the design of the Doherty presented in this paper, with the relative bandwidth estimation.The estimation is carried out considering as DPA approximation a class B-class B case, which permits a further simplification with a degradation of accuracy that we consider negligible for our purposes.The Z can simulated or mathematically transformed from an ABCD matrix, obtained as the cascade of the ABCD matrixes of the building blocks composing the proposed Doherty output combiner (see Fig. 3).Identical devices for main and auxiliary are considered, with optimum intrinsic load R opt , while the load impedance at the DPA common node is R L .The cascade of device parasitics and matching network forms an equivalent impedance inverter, with impedance Z 0 = (2R L R opt ) 1/2 , on both main (ABCD M ) and auxiliary (ABCD A ) branches.On the auxiliary side, an additional 90°delay is needed (ABCD ADD ), with impedance 2R L , to null the impedance inverting effect due to auxiliary device parasitics and matching network.The choice of using a 180°cascade network for the auxiliary output is driven by the difficulty, in the presence of series parasitics, of realizing a 0°output that would probably further benefit the bandwidth.As shown in [6], the device output equivalent network can be approximately considered as a current generator shunted with an output capacitance C OUT , and in series with an output inductance L OUT [see Fig. 4(a)].In our approach, the impedance Z 0 is selected as where f 0 is a reference frequency that corresponds to the center frequency in a narrowband design, while it can be optimized for bandwidth maximization in a broadband design.The values of C OUT and f 0 determine univocally Z 0 and, as a consequence, R L = Z 2 0 /(2R opt ).Being R L a real load, it can be matched to the external 50 impedance on a very broad bandwidth by means of multisection matching.The Z 0 impedance inverter can be implemented as a low-pass filter [see Fig. 4(b)], completing it with a series inductance L S with impedance value and another shunt capacitor with value C OUT .
In our case, a distributed solution has been preferred for implementation in a microstrip circuit [see Fig. 4(c)] using a short piece of line with arbitrary impedance Z 1 and electrical length θ 1 = sin −1 (|Z S |/Z 1 ) to implement the series inductance, and an open stub with arbitrary impedance Z 2 and electrical length θ 2 = tan −1 (Y 0 Z 2 ) to implement the shunt capacitance.ABCD M can be built by cascading the elementary ABCD matrixes of C OUT , L OUT , the series line, and the shunt stub, while the reverse order must be followed to evaluate ABCD A .
The additional 90°delay line on the auxiliary side is implemented by means of a transmission line with impedance 2R L and quarter-wave length at f 0 .This delay line works as an auxiliary offset line, showing an high impedance when the auxiliary is turned OFF, but not affecting the impedance matching at saturation [23].At the input, after a splitter with no delay difference between the output ports, a 50-transmission line on the main side imposes a φ = (π/2)( f / f 0 ) to provide a perfect phase balance of output currents at f 0 .
In the proposed combiner topology, the available free parameters that can be tuned or optimized to maximize the bandwidth are f 0 , Z 1 , and Z 2 , while the other parameters are derived using the equations of this section.

III. SPECIFIC CASE DESIGN
The proposed power amplifier is based on the CGH40010F GaN HEMT from Wolfspeed.The bias voltage is V DD = 28 V,  and the estimated knee voltage is V K = 3 V.For this design, an optimum intrinsic load R opt = 30 is selected as target for the design, since it gives a good compromise between output power and efficiency.However, the device is able to deliver a maximum current I MAX = 2 A, which is the parameter used in the bandwidth estimation and design formula.The values of equivalent output reactive components, already successfully adopted in previous designs [6], are C OUT = 1.275 pF and L OUT = 0.653 nH.
The values of f 0 , Z 1 , and Z 2 have been tuned to maximize the bandwidth with the goal to cover most of the LTE bands, i.e., from 1.6 to 3.5 GHz.The value of f 0 eventually results in 3 GHz, that leads to Z 0 = 41.6 and R L = 28.9 .The impedance of the series transmission line Z 1 tends to high values for maximum bandwidth, but it is limited in practice by the device drain pin width, and is set at Z 1 = 54 .The impedance of the open stub Z 2 results in 31 .The remaining parameters, which are obtained following the formulas in Section II-B, are reported in Fig. 5, where a full diagram of the designed DPA combiner is sketched.
After the total Z matrix is derived from the global ABCD matrix (see Fig. 6), the values of σ and V sat,M = V sat,A can be calculated according to ( 4) and ( 6), respectively, and are reported versus frequency in Fig. 7. σ (black solid curve), V sat,M (gray solid curve), and V sat,A (black dotted curve) versus frequency.As a successive step, β and V OBO,M are calculated according to ( 8) and ( 9), and are reported in Fig. 8.
The maximum output power defines F P , and is reported in Fig. 9. Considering an output power target of 1 dB lower than the nominal power delivered by two devices, i.e., P OUT,target = 42 dBm, then F P = [1.35GHz, 3.18 GHz] that corresponds to a relative bandwidth of 81%.The range F L is derived looking at Fig. 10, where the difference between OBO and IBO is reported.Assuming to be able to accept a maximum difference of 2 dB, then F L = [1.45GHz, 3.6 GHz].The alternative bandwidth estimation is F P ∩ F L = [1.45GHz, 3.18 GHz] that corresponds to a 75% relative bandwidth.
The efficiency can be only roughly estimated, especially in terms of absolute values, at each frequency point, as the ratio between RF output and dc absorbed power.A reduction of around 0.5 dB can be considered for output network losses, while at the back-off condition, another 0.5 dB can be added to account for the early turning ON of the auxiliary  device, necessary to ensure reasonably flat gain response.The estimated efficiency, at saturation and back-off, is reported in Fig. 11.It is important to note that this estimation is based on very strong assumptions, so nonlinear simulations are necessary to effectively predict the efficiency performance.

IV. MICROSTRIP DESIGN AND SIMULATIONS
The distributed elements composing the DPA output combiner have been substituted by microstrip elements, with a 760-μm Taconic substrate ( r = 3.5).The overall schematic of the DPA is shown in Fig. 12.The output matching from the common impedance of 28.9-50 is based on a two-section quarter-wave matching, modified to include the drain bias feed network.
The nonlinear model of the device, provided by the foundry, has been used in the design of the input matching and splitter, and in the tuning of the DPA before fabrication.In particular, the fine tuning permits to maintain the bandwidth performance in the passage from the much simplified model of the theory to the nonlinear model.Fig. 13 compares the load at the main device intrinsic plane, when the auxiliary is turned OFF, for different implementations of the output combiner.In particular, it can be noted that the translation from ideal lines to microstrip has negligible impact on the load.Moreover, the load trajectory of the theory-based circuit is only slightly modified by the fine tuning of the output combiner based on large signal simulations, meaning that it represented a good starting point for the design.
The input matching networks of the main and auxiliary stages are based on the same topology [24], but small differences in the components' values were adopted for an  optimized operation.The choice of the input splitter is critical for its influence on bandwidth, efficiency, and linearity.Since the main goal of this design is bandwidth optimization, an even Wilkinson divider is preferred for its ability to maintain equal and controlled splitting on a broad band.To alleviate the gain compression issue that arises in AB/C Doherty PAs with the same devices and even splitting [25], the auxiliary gate bias is adjusted in nonlinear simulations and brought closer to class B than what expected from theory, thus trading off back-off efficiency for linearity and bandwidth.A 50-delay line is inserted at the main device input to equalize the phase delay at the common node.
The DPA simulated performance versus CW frequency is resumed in Fig. 14, at a constant input power of 35 dBm.The maximum output power is higher than 42 dBm from 1.5 to 4 GHz, while the back-off efficiency is higher than 30% from 1.7 to 3.9 GHz.

V. CHARACTERIZATION RESULTS
The scattering parameters of the fabricated DPA (Fig. 15) have been measured on the range 1-4.5 GHz for an initial assessment of the device performance.The applied bias is V DD = 28 V, with a main device quiescent current of I DD = 100 mA, and auxiliary device gate at −5 V.The agreement between simulations and measurements is rather good, with a slight frequency shift to lower frequency of the measured S 21 .
The DPA has been characterized with CW single-tone input in the 1.5-3.9GHz range, with a 100 MHz step.Fig. 17 summarizes the measured CW performance at saturation and back-off versus CW frequency.On the 1.5-3.8-GHzband, the saturated output power exceeds 42.3 dBm, with the associated efficiency in the range 42%-63%.The saturated power is considered in the range of 2-4-dB gain compression, in order to account for the 2-dB maximum compression defined for F L , plus the compression due to the intrinsic nonlinear behavior of the active devices.At 6-dB back-off, the efficiency remains between 33% and 55%, while the small-signal gain is higher than 10 dB, with a ripple of 1.9 dB.The measured results are in good agreement with the simulation in Fig. 14, and the achieved bandwidth is well predicted by the proposed estimation method.Fig. 18 shows the CW power sweeps at 1.6, 2.1, 2.6, and 3.5 GHz.
The measured CW results are resumed in Table I and compared with other broadband DPAs presented in the literature.The proposed DPA has larger bandwidth, both in absolute and fractional terms, and similar output power and back-off efficiency compared with the other DPAs.
The DPA has been characterized with a modulated signal to assess its linearity and linearizability.The measurement setup is shown in Fig. 19.The RF modulated signal is generated by an arbitrary waveform generator (Keysight   ESG4433B), amplified by a driver amplifier, fed to the DPA, and then detected by a vector signal analyzer (Keysight MXA N9020A).A digital predistorter, based on a memory polynomial model [26], is implemented in MATLAB and is applied to improve linearity and average efficiency.The predistorter has an odd polynomial order P and finite impulse response filter order M.
The measured spectra, before and after applying the predistorter, are shown in Fig. 20.At 2.6 GHz center frequency, a 7-MHz channel WiMAX signal with a PAPR of 9 dB has been applied, resulting in an ACPR of 42 and 48 dB, before and after predistortion (P = 5 and M = 2), respectively, at an average output power of 34 dBm and average efficiency of 33%.

VI. CONCLUSION
A state-of-the-art broadband DPA has been designed using a new approach, supported by a simplified analysis for the initial bandwidth estimation.The power amplifier has been fabricated using packaged GaN HEMT devices.On the band 1.5-3.9GHz, corresponding to a fractional bandwidth of 87 %, the amplifier showed a maximum output power higher than 42.3 dBm, with a saturated efficiency between 42% and 63%, and 6 dB back-off efficiency between 33% and 55%, hence representing, to the best of our knowledge, the state of the art in broadband DPAs.

Fig. 6 .
Fig. 6.Z parameters versus frequency in the specific design case.(a) Real part.(b) Imaginary part.

Fig. 9 .
Fig. 9. P OUT,sat versus frequency.The range F P is shaded.

Fig. 12 .
Fig. 12. Electrical scheme of the designed DPA.Lengths and widths are in millimeters.

Fig. 13 .
Fig.13.Simulated load at the main device intrinsic plane, when the auxiliary device is turned OFF, in the 1-4.5-GHz band.Doherty output combiner with ideal lines (black solid curve), microstrip (light gray solid curve), and microstrip after fine tuning with nonlinear model (dark gray dashed curve).

Fig. 16
Fig.16shows the measured and simulated S 21 , S 11 of the DPA; the measured gain is higher than 10 dB from 1.45 to 3.8 GHz.The agreement between simulations and measurements is rather good, with a slight frequency shift to lower frequency of the measured S 21 .The DPA has been characterized with CW single-tone input in the 1.5-3.9GHz range, with a 100 MHz step.Fig.17summarizes the measured CW performance at saturation and back-off versus CW frequency.On the 1.5-3.8-GHzband, the saturated output power exceeds 42.3 dBm, with the associated efficiency in the range 42%-63%.The saturated power is considered in the range of 2-4-dB gain compression, in order

TABLE I COMPARISON
WITH OTHER SINGLE-INPUT BROADBAND DPAS Fig. 16.Scattering versus frequency of the fabricated DPA.Symbols: measured.Solid lines: simulated.Black squares: S 21 .Gray circles: S 11 .