A Reappraisal of Optimum Output Matching Conditions in Microwave Power Transistors

This paper presents a novel approach to the identification of output power and efficiency contours in microwave power transistors in compressed regime. The formulation is based on a polynomial representation of the drain–source voltage profile accounting for the knee region. Closed-form equations for the output power and efficiency as function of the fundamental load are demonstrated, enabling the plot of contours on a Smith Chart. From these, a further simplified drawing procedure for approximated contours is also derived, differentiating between two families of output characteristic. The first, with smooth knee, is usually experienced in GaN devices, while the second exhibits a steep knee which can be associated with GaAs devices’ typical behavior. A 5-W GaN HEMT, a 2.5-W GaN HEMT, and a 0.7-W GaAs pHEMT are characterized with load-pull measurements. In all the three cases, the proposed method results in a very accurate contour construction, despite being based on an approximated output current/voltage profile and on a rough estimate of output equivalent capacitance.

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A Reappraisal of Optimum Output Matching Conditions in Microwave Power Transistors
Roberto Quaglia, Member, IEEE, Daniel J. Shepphard, Student Member, IEEE, and Steve Cripps, Life Fellow, IEEE Abstract-This paper presents a novel approach to the identification of output power and efficiency contours in microwave power transistors in compressed regime.The formulation is based on a polynomial representation of the drain-source voltage profile accounting for the knee region.Closed-form equations for the output power and efficiency as function of the fundamental load are demonstrated, enabling the plot of contours on a Smith Chart.From these, a further simplified drawing procedure for approximated contours is also derived, differentiating between two families of output characteristic.The first, with smooth knee, is usually experienced in GaN devices, while the second exhibits a steep knee which can be associated with GaAs devices' typical behavior.A 5-W GaN HEMT, a 2.5-W GaN HEMT, and a 0.7-W GaAs pHEMT are characterized with load-pull measurements.In all the three cases, the proposed method results in a very accurate contour construction, despite being based on an approximated output current/voltage profile and on a rough estimate of output equivalent capacitance.

I. INTRODUCTION
I T HAS long been recognized that loadline considerations can be used to design power amplifiers at higher frequencies, so long as the impedance reference plane is set at a conceptual point which lies "inside" the device output parasitics [1]- [3].Over thirty years ago, one of the present authors [3] showed how the basic loadline method could be extended to take account of reactive loads and as such showed how plausible "load-pull contours" could be constructed with minimal large-signal power measurements.This analysis, however, made several simplifying assumptions; in particular, it only accounted for situations where the device plane voltage swing remained outside of the I -V "knee" region.This assumption is especially restrictive for cases where the device is presented with an impedance whose magnitude is higher than the loadline resistance.Nevertheless, the technique in [3] has been widely and successfully used for the design of linear RF power amplifiers (RFPAs) operating up to, but not beyond, the 1-dB compression point.
Other approaches have been pursued to approximate the optimum load conditions without relying on large-signal measurements or models.The simple model proposed in [4] explicitly includes device parasitics to predict the contours at different frequencies.The work presented in [5] uses a small signal equivalent model to extract a first approximation of class-A power amplifier (PA) optimum power loads.It takes into account the voltage/current device limitations, in this case a GaAs pHEMT, by imposing elliptic dynamic I -V curves tangential to the maximum current/voltage limits.The methodology of [3] is extended to Cascode stages in the work presented in [6].
The need to predict, at least in a first approximation, the efficiency of the PA for varying load has become particularly important for the design of Doherty amplifiers.In fact, the simplistic assumption frequently made in the literature that constant efficiency can be maintained using the textbook load modulation has been shown to be inaccurate; this is due in part to the knee clipping of the device current during the entire load modulation regime.In [7], this phenomenon is explained relying on a simplified device (LDMOS in this case) model taking into account for R ON and for the smooth turn-ON of the transcharacteristic.The proposed model in [7] is able to accurately predict power and efficiency contours in linear operation (around 1-dB gain compression), as it has been refined and extended to higher power LDMOS transistors in [8].On the other hand, the different knee interaction for varying load can be exploited, as shown by [9] and [10], to increase the average efficiency of the Doherty PA.
Recently, some advanced PA architectures that intentionally drive the device into the saturated region have been reexamined as candidates for highly linear RFPA applications.For example, the Chireix outphasing PA is receiving renewed attention, largely due to the now widespread use of digital signal processing and the consequent ability to generate complex baseband and IF signal formats [11].Moreover, numerous nontelecom applications often make use of PAs with devices operated well into saturation.As such, this paper addresses a need for a more generic theory that characterizes the power and efficiency behavior of an RF power transistor that may include operation well into the clipping, or saturation, region.The approach, however, still attempts to retain the simplistic spirit of the original analysis in [3], and it is based on the approximation of the I -V output characteristics by means of a polynomial.This paper is organized as follows.Section II explains the applied approximations and derives the closed-form equations for output power and efficiency.Section III uses the obtained equations to analyze the variational trends of optimum power/efficiency loads for different knee profiles, and proposes a further simplified method for graphically build-This work is licensed under a Creative Commons Attribution 3.0 License.For more information, see http://creativecommons.org/licenses/by/3.0/Fig. 1.Knee profile versus v ds for N = 4 (light gray), 6 (gray), 8 (dark gray), and 24 (black).
ing the contours.Section IV reports the comparison between estimated and measured power/efficiency contours for GaN and GaAs devices.Finally, Section V draws some conclusions.

II. BASIC CONCEPT
Loadline-based PA design of a tuned class-B amplifier defines the optimum load for output power as R opt = 2V DD /I MAX ,w h e r eV DD is the drain bias voltage, and I MAX is the maximum of the truncated sinewave that represents the drain current.In a normalized representation, where V DD = I MAX = 1, R opt results equal to 2, the maximum output power is (V DD I MAX )/4 = 0.25, and the maximum efficiency is π/4.In this paper, the normalized drain current is defined as where A() is the baseline function, determined as the transconductance function applied to the input voltage, thus a periodic function of the angle θ , while k() describes the knee as the function of the normalized drain-source voltage v ds .
A simple polynomial form is used for k() where N is an even integer identifying the polynomial order.T h ep r o fi l eo fk() is shown in Fig. 1, for different N values.
For N that tends to very high values, function tends toward the "text book" approximation of zero knee voltage.A realistic approximation of a typical GaN device behavior is obtained with 4 ≤ N ≤ 8, while a higher N should be adopted for GaAs devices (e.g., N > 20).It is important to notice that the knee profile to be approximated must refer to a pulsed I -V measurement or a dynamic RF "fan diagram," to account for dispersion and thermal issues.The fan diagram is a collection of dynamic load line measurements on different intrinsic resistive loads that highlights the profile of the knee [12].The formulation of ( 2) is particularly convenient when assuming short-circuited harmonics, writing v ds as where V and φ are free parameters that can be swept to simulate arbitrary complex terminations at fundamental.If harmonic loads are not short circuited, as in the case of exploiting different PA classes [13], it is not possible to identify unequivocally the voltage waveform shape, and a numerical approach may be followed for the determination of the contours [14].With shorted harmonics, the knee description becomes Two examples of current profiles are shown in Fig. 2, with V = 0.9a n dφ = 0a n dV = 0.8a n dφ =− (π/8), N = 4, 6, 8, and 24, and assuming a class-B baseline current.Notice that V can be actually pushed slightly above 1 to emulate very compressed behavior of the transistor [15].An important consideration to be drawn is related to the nonphysical behavior of the polynomial function when v ds ≫ 1, that corresponds to k(v ds ) approaching zero for v ds = 2.The impact of this approximation will be negligible for |φ| close to 0, when considering class-B or deepclass-AB cases, since the current baseline function A() is also very close to zero in that output characteristic region.For |φ| approaching (π/2), an error in the evaluation of dc and fundamental components of current is present.However, the amount of this error is very low, even for low N, and will only result in a limited distortion of contours in the extreme cases of highly reactive loads that are seldom exploited in PA design.
The knee function of (4) can be expanded in The k j terms are functions of (V,φ) The terms N N/2 are a binomial form.If the current baseline function A() is even, as normally assumed in theoretical PA analyses, it can be expanded as The dc and fundamental components of i ds result, after some rearrangement, as Writing the fundamental voltage and current in phasor form allows evaluating output power, efficiency, and load Now, for each current and knee profile, it is possible to trace power and efficiency contours by sweeping the (V,φ) values.Fig. 3 shows the power and efficiency contours, obtained with a truncated sinewave for the current, class-B bias, and for knee polynomial orders of N = 4, 6, and 8.The Smith chart normalization impedance is R opt = 2. Calculations are performed in MATLAB using the expressions ( 6)- (10), and the contours are traced with the native contour function.Fig. 4 reports the same type of contours but evaluated for N = 16, 24, and 32, representing realistic knee approximations for GaAs devices.It can be seen that the obtained power contours are distinctly noncircular, and that they converge for increasing N. Fig. 5 reports the contours for N = 1000, where the polynomial knee function tends to an ideal abrupt knee function, compared with the contours proposed in [3].On the left Smith chart quadrants, the contours are identical, being the region not affected by current clipping; the impedance magnitude is lower than that required to cause the voltage to reach the knee region.Since the current is unclipped, power and efficiency contours are coincident.On the other hand,  the right-hand quadrants show significant separation of power and efficiency contours due to the current clipping effects.Although this has been cited as a flaw in the theory proposed in [3], this difference is mainly due to the fact that the contours in [3] were defined by reducing the maximum current so as not to clip the waveforms, thus avoiding any knee effect.So this discrepancy in fact only applies to efficiency; the clipped (right-hand) power contours are quite close to the original circular arc proposed in [3]; this is somewhat fortuitous inasmuch as the derivation in [3] was based on backedoff current swing rather than the clipped current waveform analysis.

A. Locating Maximum Values and Optimum Loads
By observing the contour plots in Figs. 3 and 4, it can be seen that the maximum for power (P max ) and efficiency (η max ) always correspond to loads R p and R η on the real axis, i.e., to φ = 0.This is consistent with the previous results on tuned load PAs [8], [16].It can be demonstrated that, for φ = 0, the output power and the efficiency can always be written as The real coefficients a, p, b,a n dd are function of N and of the baseline current waveform.The value of V that maximizes the output power (V = V p ) and the efficiency (V = V η ) can be determined after equating to 0 the derivative of ( 11) This results in where t is the only solution to the second-order polynomial 1−((N + 1) p − (N − 1)d) t + pdt 2 giving positive dc current.Once V p and V η are known, the corresponding real loads can be calculated.Fig. 6 reports the values of P max ,η max , R p , and R η versus knee order N, considering a class-B current baseline waveform.As expected, for N that tends to very high values, R p and R η tend to converge to R opt = 2, and the values of P max and η max achieve their theoretical limits of 0.25 and π/4, respectively.For 4 ≤ N ≤ 8, R p is around 1.9, and R η is around 1.5-2 times R p .

B. Construction of Approximated Contours for Smooth Knee Devices
The proposed method permits to build the contours solving few equations.However, a further simplification is possible by graphically approximating the contours, enabling an even simpler implementation of this method in a CAD environment.From Fig. 3, it can be seen that efficiency contours for low values of N, typical of GaN devices, can be reasonably approximated by circles centered on the real axis.To determine the center and radius of these circles, it is sufficient to know the intersections with the real axis that can be found as the real roots to the following N + 1 order polynomial equation: The coefficient α, in dB, determines the level of the efficiency contour.The obtained solution in V variable leads to two points on the Smith chart, assuming a normalization impedance of R opt = 2. Conversely, the power contours are not well approximated by circles, but they result more similar to ellipses with the vertical axis (y-radius) longer than the horizontal one (x-radius).The center and the horizontal radius of the ellipse can be found in a similar manner to the efficiency contour derivation, by solving the equation Vertical radius can be found by locating the points on the contour where the real part of Ŵ equals the ellipse center.
Considering a class-B truncated cosine as current baseline, the center and radii for N = 4, 6, and 8, and different α values are reported in Tables I and II for efficiency and power, respectively.

C. Construction of Approximated Contours for Steep Knee Devices
For the approximation of contours when N is large, for example, around 24 for GaAs devices, ellipses can still be used for power contours.The center and the axis-radii, indicated in Table III, have been extracted graphically.
Efficiency contours for N = 24, as can be seen in Fig. 4, can be approximated combining a partial ellipse (on the left hand) and a partial circle (on the right hand), whose centers and radii are reported in Table IV, and have been graphically approximated.

D. Guidelines for Contours Drawing
Following the results of Sections II and III, a procedure for contours drawing can be identified as follows.
1) Identify N by analyzing the output I -V characteristics from pulsed I -V or fan diagram measurements.2) Draw the normalized power/efficiency contours using the equations of Section II or the tabulated values of this section.3) Denormalize the contours to the estimated R opt .4) Account for the frequency dispersion by rotating the contours on the Smith chart according to the parasitic/package definition.This last step is actually very important.In fact, if strong nonlinear capacitive effects are present, nonlinear embedding procedure must be applied to properly move the reference plane from the intrinsic current generator to the device tabs [17], [18].

IV. EXPERIMENTAL RESULTS
The simplified contour drawing procedure is tested and compared with load-pull characterization results for all the three devices using the Cardiff University harmonic source/load-pull setup.The measurement setup block diagram and photograph are shown in Fig. 7 consisting of a real-time, two-port, source/load-pull measurement system [19].Active harmonic source/pull strategy is adopted, with frequency multiplexers enabling the independent behavior of the different source/load-pull harmonic sources.The use of a large-signal vector analyzer, and of a comb-generator as reference for phase realignment of harmonic components, enables the measurement of the waveforms at the device-under-test (DUT) plane [20].The system is computerized and controlled by ad hoc software.
The three devices are as follows:   Fan diagram measurements [12] on the devices are shown in Fig. 9, together with the selected k() functions with N = 4, N = 6, and N = 24 for the GaNFET1, GaNFET2, and GaAsFET case, respectively.
The GaNFET1 device has been measured at 3 GHz, with drain bias voltage of 28 V and quiescent current of 15 mA.The GaNFET2 device has been characterized at 2 GHz, with drain bias voltage of 20 V and quiescent current of 5 mA.The GaAsFET has been characterized at 2 GHz with drain bias of 10 V, 10 mA.A constant input drive, corresponding to roughly 3-dB compression at the optimum power load, is applied.For a proper comparison with the theory, the second and third harmonics are shorted on the device terminals.For the GaNFET1 device, the maximum measured output power is 5.4 W, while the maximum efficiency is 63%, reasonably in agreement with the estimation provided by Fig. 6, from which 5 W and 65% are expected, respectively.The intrinsic optimum load for output power is around 55 , slightly higher than the estimated value.For the GaNFET2, the maximum measured output power and efficiency are 2.4 W and 58%, respectively.The output power is in good agreement with Fig. 6, that estimates 2.5 W, while the efficiency is lower than expected, probably related to the immaturity of the process.In this case, the measured intrinsic optimum load for output power is 55 , very close to the expected 51 .Regarding the GaAs device, the maximum measured output power and efficiency are 0.72 W and 72%, respectively, again in good agreement with Fig. 6, that estimates 0.7 W and 74%, respectively.In this case, the measured intrinsic optimum load for output    contours, shifted to the external device plane using the equivalent capacitances, and the measured ones.The reflection coefficient error between the measured and computed contours is always lower than −19 dB.
Similarly, Figs. 12 and 13 compare the measured contours with the ones constructed using the approximated shapes of the tables of Section III.As can be seen, the approximated contours show good agreement with the measured ones, and the error of the reflection coefficient is always lower than −19 dB.

V. C ONCLUSION
In this paper, a novel and simple method to estimate power and efficiency contours in microwave power transistors has been proposed.Closed-form equations for power and efficiency in saturation regime, using a polynomial approximation of the device's output characteristics, have been derived.While any contour level can be obtained through the solution of the proposed equations, approximated contours have also been proposed based on simple shapes as circles and ellipses.Center and radii at some significant contour levels, for devices exhibiting either a smooth or a steep knee, are tabulated for a fast reference.The contour drawing procedure does not require, at least in principle, microwave large-signal measurements, and represents a useful tool for power amplifiers design.

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Fig. 7 .
Fig. 7. (a) Block diagram and (b) photograph of the adopted active source/load-pull setup.

TABLE I CENTER
AND RADIUS FOR APPROXIMATED EFFICIENCY CONTOURS IN Ŵ TABLE II CENTER AND RADII FOR APPROXIMATED POWER CONTOURS IN Ŵ

TABLE III CENTER
AND RADII FOR APPROXIMATED POWER CONTOURS IN Ŵ FOR N = 24 (OR SIMILAR STEEP KNEE APPROXIMATION)

TABLE IV CENTER
AND RADII FOR APPROXIMATED EFFICIENCY CONTOURS IN Ŵ FOR N = 24 (OR SIMILAR STEEP KNEE APPROXIMATION)