Direct Interface Circuit for Capacitive Sensors Affected by Parasitic Series Resistances

This article presents a novel circuit to directly interface a capacitive sensor affected by parasitic series resistances to a digital processor (DP). The presence of such resistances distorts the estimation of the capacitance to be measured. Current measurement procedures for these sensors, such as impedance-frequency characteristics, are complex and require significant hardware resources, power consumption, and time. To eliminate these drawbacks, a new circuit based on the so-called direct interface circuits (DICs) is introduced, which performs the digital reading of the sensors taking advantage of the presence of DPs in many applications. The hardware requirements in the new design are minimal: just two resistors and an operational amplifier in addition to the DP. The circuit requires only two time measurements to estimate sensor capacitance. These are obtained during a single capacitor charging-discharging process, simultaneously reducing power consumption and measurement time. The circuit has been implemented using a field-programmable gate array (FPGA), as the DP, in a general-purpose board to evaluate its performance. Although it is not an application-specific design, the circuit shows a maximum systematic error of 0.37% for capacitances in the 100 pF–96 nF range with parasitic series resistances up to 1200 $\Omega $ . The maximum measurement time for this range is just 4.5 ms.


I. INTRODUCTION
T HE explosion of the Internet of Things (IoT) and ambient intelligence (AmI) applications are changing perspectives around the design of sensor reading circuits. These applications require small, inexpensive, and reliable circuits with as few components as possible. IoT or AmI is often used in mobile or standalone devices with small batteries, meaning reduced power consumption is also a significant goal for any circuit designer for such applications. Naturally, the circuits must also be fast enough to provide real-time information about their environment. Finally, since IoT and AmI form part of a digital world, readings from these circuits should also be provided in digital format. One attractive option to meet all these specifications is to use the digital processors (DPs) found in many IoT or AmI applications as part of the readout circuit. This is the basis of the direct interface circuit (DIC) concept introduced some years ago. In this type of circuit, the sensor is connected directly to the DP [either a microcontroller, an ASIC, or a field-programmable gate array (FPGA)] with a minimum number of additional components without needing an analog-to-digital converter (ADC). All DICs are based on a magnitude-to-time-to-digital conversion. Magnitude-totime conversion is carried out due to a few extra components included in the circuit. These components could be just passive elements or include some operational amplifiers (OAs) and switches, but such active components are always very limited in number. Finally, it is the DP itself that performs the timeto-digital conversion. Some DICs measure purely resistive sensors [1], [2], [3], purely capacitive sensors [4], [5], and purely inductive sensors [6]. We can also find DICs for reading differential resistive sensors [7], [8], differential capacitive sensors [9], [10], or differential inductive sensors [11], as well as DICs, to read lossy capacitive sensors that present a parasitic shunt resistor with the capacitive sensing element [12], [13]. In symmetrical situations, with a resistive sensor affected by a parasitic parallel capacitance, we can use, for example, the DIC proposed in [14].
One problem that can appear in reading different sensor circuits is the existence of parasitic series resistances attached to the sensor. We will call these resistances R S . This occurs, for example, due to the contact resistances needed to implement the circuitry and can be increased by the resistance of the long interconnection cables required when the sensors and readout circuitry are separated in different environments.
In the case of resistive sensors, parasitic resistances R S can cause large differences between the resistance value measured when using the circuits proposed in [1], [2], and [3] and the real information provided by the sensor (especially if the resistance values to be measured are small). To solve this issue, resistive DICs based on the well-known three-wire technique have been used in [15] and [16]. We can also find DICs that address this problem in the literature using the four-wire technique, as in [17] and [18]. It is also possible to apply the concept of DIC to remote resistive sensors with a two-wire connection [19], [20], where two diodes and several switches are added to the circuit to obtain the resistance value. The presence of nonlinear elements forces the range of values to be measured to be small, limiting the use of these circuits.
However, R S can also appear in the case of capacitive sensors. In this case, R S can be due to long wires connecting a distant capacitive sensor to the DP, but in the case of capacitive sensors close to the DP (or inside it, as can happen in an ASIC), R S may be due to manufacturing processes This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ (long interdigitated electrodes, materials used, contacts, etc.) or by the very nature of the physical mechanisms on which capacitive sensors are based. In the latter case, R S is commonly known as charge transfer resistance, R CT [21], and their values are not always provided due to the difficulty of their measurement. These resistances can be associated with a single sensor terminal or both, as shown in Fig. 1 (in this last case, R S is the sum of R S1 + R S2 ).
The capacitive sensor's configuration with two parasitic series resistors is shown in [22], where a textile-mounted capacitive soft-strain sensor is introduced to identify elongational strains. Due to the device's construction process, each sensing electrode is connected to a different parasitic resistance, which can be in the kiloohm range, while the capacity can reach 100 pF. Contact resistors can be seen in [23], where a capacitive pressure sensor is designed for integration in clothing to measure pressure on the human body (no R S values are given, however). They also appear in capacitive sensors for tactile sensing in an electronic skin [24] with values around 400 . The configuration with just one series resistor can be seen in the capacitive immunosensor presented in [25]. In this case, sensor capacitance, C X , is in the range of 100 pF-100 nF, and R S is in the range of a few hundred ohms. The same configuration appears in [21], where a humidity sensor with capacitances varying in the 80 pF-8 nF range is presented (no data on R S values are provided either). Finally, Luo et al. [26] show a capacitive pressure sensor with Au/PET electrodes, whose capacitance varies around 200 pF.
On the other hand, liquid-level sensors [27], [28] are typical applications with remote capacitive sensors that have parasitic series resistances due to wiring (in [27], C X ranges between 2 and 10 nF and in [28] between 400 pF and 1.8 nF).
The works in [22], [23], [27], and [28] do not show any method to correct errors in the estimates of C X due to the presence of R S , even though Meyer et al. [23] report the errors of up to 20% in the estimate of C X due to these resistances. In [24] and [25], C X estimates are corrected by performing tedious impedance-frequency analysis. While solving the problem, this technique requires complex circuitry and significant time investment. For example, Prasad and Lal [25] require a lock-in amplifier, a voltage-to-current converter, and a digital multimeter, all controlled by external software to carry out the impedance-frequency analysis. To the best of our knowledge, no DIC has been reported in the literature to measure a capacitive sensor with parasitic series resistances, despite the apparent benefits such circuits can bring.
This article presents a new DIC circuit that can measure the capacitance, C X , of a capacitive sensor in the presence of parasitic series resistances (whatever the cause of the existence of these resistances), eliminating this source of error in the estimation. As with any DIC, the new proposal consists of a few elements apart from the DP. The circuit estimates C X quickly since it only needs a single sensor charging-discharging process to obtain the two time measurements required. For the same reason, power consumption and measurement time are significantly reduced, making the new circuit an ideal candidate for IoT or AmI applications.

A. Description of the Method and Circuit Analysis
The new circuit is shown in Fig. 2. Although the capacitive sensor shown in this figure is for the two-resistor configuration shown in Fig. 1, the circuit can be used with either configuration simply by substituting R S1 or R S2 for a short circuit. The description of the operation to be performed is valid for both configurations.
The P A and P B pins of the DP in Fig. 2 must be tristate pins, so they can be configured as an input or output. In addition, when configured as inputs, they mus have a very high input impedance, which we denote as HZ (this is not a very restrictive condition, as most DPs currently meet this requirement). Thus, if a pin is configured as an input, we will indicate it as HZ. The P m pin must also be a tristate pin, although the pin is optional, as explained in the following. P Sd and P In are the output pins in any situation.
The values of C X and the characteristics of the pins configured as outputs should prevent the current charging the capacitor from being high for a long time (although this can be easily avoided by inserting a low-value resistor between P m and the inverting input of the OA, if necessary).
The circuit has an OA with shutdown mode. The V Sd input connected to P Sd selects this mode. If V Sd is a logical 0, the OA is in shutdown mode with the output in the HZ state. If V Sd is a logical 1, the OA works in its regular operating mode. For the sake of simplicity, it is considered that the logic levels V OL and V OH correspond to power supply voltages 0 and V DD of the DP, respectively. This assumption does not affect the reading method, and it only modifies the maximum voltage differences between the capacitor's terminals. Using an OA  with shutdown mode helps reduce power consumption when a sensor reading is not performed. If the OA is a rail-to-rail input and output type, its supply voltages can be V DD and 0, as for the DP.
As mentioned above, only a single charging-discharging process is required to obtain the time measurements to estimate C X . The circuit pins configuration in the steps needed to complete the process is shown in Table I. The temporal evolution of signals V A and V B in Fig. 2 in each of these steps is shown in Fig. 3 (the steps for Table I are shown at the top of Fig. 3 with numbers in the gray box).
In the first step, charging C X , the OA is brought to shutdown mode by selecting P Sd = "0." At the same time, C X is being charged to a V DD voltage, providing a logical 1 output in pins P A and P B and setting P m and P In to "0." It should be noted that the P m pin is not required to charge the capacitor, as this can be done using just P In . However, if R In in Fig. 2 has a high resistance value, the charging process may take too long if P m is not present. The designer must consider this when deciding whether to include P m or not. Since the only function of the P m pin is to make C X charge faster, it can be dispensed with in applications that do not require a high data acquisition rate. The length of the charging process is shown in Fig. 3 as T ch .
Once the sensor is charged, the second step, activating the OA, is carried out by selecting P Sd = "1." In this second step, P A , P B , and P m (if present) also change to HZ state while maintaining P In = "0." Since the OA needs time to function correctly from the instant that V Sd becomes "1," this step must have a minimum duration, T on , shown in Fig. 3. This time depends on the selected OA model. The third step, discharging C X , is carried out once the OA is activated. This step only involves changing P In = "1" (this instant corresponds to t = 0 in the equations describing the discharging process). Now, the current entering the left terminal of the capacitor, I In in Fig. 2, initiates the discharge of C X .
In the third step, pins P A and P B detect the instant when voltages V A (t) and V B (t) reach the value V TL (trigger instant).
V TL is the threshold voltage to detect a logical 0 input in the P A or P B pins, starting from a logical 1 input level. It is important (1) Hence, V A (t) > V B (t) throughout the discharge. In consequence, to guarantee the correct operation of the circuit, such that the DP detects V A and V B as "1 s" at the start of the discharge process, it is enough to ensure that Condition (2) must be written in an alternative form to ensure that it is handled correctly by the designer. To this end, if R In has a sufficiently large value (R In much larger than the output resistance of a pin), we can write Moreover, if R AB is chosen much larger than any expected value of R S , (1)- (3) give us the relationship the designer must fulfill V TL may change slightly with the circuit's operating conditions and aging, and R S has also been neglected in (4). Thus, the chosen values of R AB and R In should provide sufficient safety margin to verify (4) under all circumstances [two-or three-tenths of the difference between both sides of (4) is enough, as will be seen in Section III]. In any case, V DD or V TL does not need to be known precisely, nor is it necessary to know the value of I In .
Since I In remains constant during the discharging process of C X , V A (t) and V B (t) are given by These two equations are still valid for configurations with a single parasitic series resistor. Equations (5) and (6) describe a linear discharging process of V A (t) and V B (t), as shown in Fig. 3. These equations make it easy to find the trigger instants for V A (t) and V B (t), T A , and T B , respectively, in Fig. 3 T and from these times This is the C X estimation equation using the circuit in Fig. 2. The equation is straightforward, requiring only two time measurements and a resistance value selected by the designer to estimate the correct capacitance of a capacitive sensor in the presence of parasitic series resistances. Due to (9), C X is obtained independently of the value of R S , V TL , V DD , and I In , thus ensuring higher precision while avoiding thermal or aging drifts.
From an arithmetic perspective, (9) only needs one subtraction and one multiplication (since the admittance value Y AB = 1/R AB is stored in the DP), meaning it can be easily implemented in modern DPs. Obviously, the DP must have some timer or counter to generate T A and T B (in a number of cycles of its internal clock). Power consumption is minimal due to only a single charging-discharging process, and the OA is disabled during charging and when estimates are not needed. Finally, if necessary and as shown in Fig. 3, the circuit can immediately start a new estimation process once T A has been obtained.

B. Error Analysis
There are a variety of sources of error in the estimate provided by (9). First, one must consider the parasitic capacitors that appear in the implementation of the circuit. These elements are shown in red in Fig. 4. There are stray capacitors due to the DP pins and circuit routing C In , C m , C A , and C B . However, while C In and C m can slightly slow down the charging of C X , they do not affect its estimation. This is so because, at the beginning of the discharging, I In does not need to be constant; it is only strictly necessary that it be constant from T B to T A to obtain (9). Slight variations of I In at the start of the discharging process of C X due to C In and C m are therefore not important.
However, C A and C B affect the estimate of C X , limiting the accuracy and the lower limit of the capacitances that can be estimated by (9). This can be overcome with a simple offline autocalibration, requiring only two measurements (T A0 and T B0 ), removing the sensor in the circuit of Fig. 2. These times will give the value of a parameter, C off which, stored in the DP, offers the new estimate of C X The output resistances of the DP pins also do not matter since they only affect, to a small degree, the value of I In . For the nonideal OA parameters, the input offset voltage, V os , slightly modifies I In and the voltage stored in C X but does not affect the estimate. To verify this, we must bear in mind that (3) becomes while (5) and (6) are now T A and T B can be obtained from these two equations, proceeding as was done to obtain (7) and (8), but these times give the same result as shown in (9). The input bias current of the OA similarly does not modify (9) if constant. Finally, the output resistance of the OA does not change (7) or (8).
The situation is somewhat different for the open-loop voltage gain of the OA, A v , as linear variations with time V A (t) and V B (t), (5) and (6), are only valid if A v → ∞. If this is not the case, the relationships are exponential. However, it is also easy to check that if A v ≫ 1 and then (7) and (8) are still valid. The relationship (15) is not very limiting for the designer since, in practice, R In ≫ R S + R AB , and any commercial OA verifies A v ≫ 1. Variations in voltage V DD provided by a digital pin can also affect the performance of different DICs. This is mainly due to the estimates made by these DICs being based on time measurements in different charging-discharging processes, which implies that the voltages stored in the capacitor must be equal at the beginning of each discharge process. However, in our case, using a single charging-discharging process eliminates this source of error. On the other hand, noise at I In from T B to T A due to noise at V DD does not affect the estimate if the mean noise voltage is 0.
Also, there may be slightly different values of V TL in pins P A and P B (V TLA and V TLB ). These differences can be less than millivolts in modern fabrication processes. However, if these differences exist, (9) becomes Since the second term on the right-hand side of (16) is constant, this equation has the same form as (11). The same offline autocalibration performed to obtain (11) simultaneously compensates for the errors produced by the minor differences in V TL .
Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.
Finally, we must consider the effects of the bias current of the P A , P B , and P m pins: I BA , I BB , and I Bm , respectively. It is easy to see that I BB does not change (5) or (6), and therefore, neither does (9). I Bm only modifies the current that discharges the capacitor and passes through R AB , but it does not alter (9). However, I BA changes (6) but not (5), so that (9) becomes Thus, to continue using (9), it is necessary that The DP selected by the designer and the value of R In must guarantee the fulfillment of this condition. The best option is the selection of input pins based on standard CMOS technologies, so that I BA is reduced to the small leakage current of the pin.

C. Increasing Resolution and Uncertainty
The range of possible T A − T B values must be expanded to increase resolution in the estimate of C X using (9). This requires two simultaneous actions. First, to increase the range of values of T A and T B and, second, to increase their difference. A simple way to achieve the former is to decrease the value of I In (by increasing R In ), so more time is needed to discharge C X , as shown in (7) and (8). However, these equations also show that the only way to increase the difference between T A and T B is to increase the value of R AB .
It should be noted that increasing R AB decreases only the value of T B . The ideal situation would be one in which T B → 0 (a small value but with high resolution). Although (4) limits the maximum value of R AB , it also shows that R AB can be increased by doing the same with R In . This would suggest that any simultaneous increase in these resistance values translates into an increase in resolution. The rest of the subsection will show this mechanism's limitations.
Uncertainty in the estimation provided by (9) comes mainly from uncertainties in time measurements T A and T B , u(T A ), and u(T B ). There are two reasons for uncertainties [1], [29], [30]: quantization in clock cycles of the time measurements, which produces quantization uncertainty u q , and electronic noise in the trigger instant of V A and V B , creating trigger uncertainty u t .
The choices made by the designer to increase resolution decrease the effects of quantization, meaning we can neglect its impact by choosing sufficiently large values of R In and R AB . u t depends inversely on the slope of the discharge curve at the trigger instant [1], [31]. Thus, in our case, considering (5) and (6) where α i is a constant related to the noise level in a circuit's node.
We can find a measure of the quality of the C X estimate, u(C X )/C X , using (9) With (9) and (19), the relative uncertainties appearing in this equation can be written as follows: finally resulting in This equation has important practical implications since, on the one hand, it indicates that relative uncertainty in the estimation of C X is constant for a given choice of R In and R AB . However, it also shows that the ratio of resistance values has the same effect on uncertainty and resolution, increasing or decreasing them simultaneously.
The sequence of choice for the resistance values should therefore be 1) Choose the minimum value of R In , so T A and T B are unaffected by quantization effects. 2) Choose the highest possible value of R AB that fulfills (4). Choosing a higher value for R In and R AB makes no sense, as this only increases measurement time without improving measurement quality.

III. EXPERIMENTAL RESULTS AND DISCUSSION
The proposed circuit has been designed with an FPGA as the DP. Flexibility in design and the ability to perform tasks in parallel make these digital devices interesting options in any design. Specifically, the Artix 7 XC7A35T by Xilinx has been selected. The FPGA is included in a CMOD A7 board by Digilent (Pullman, Washington). This general-purpose board consists of a USB-UART bridge (implemented with an FT2232HQ), clock source, 512-kB SRAM, 4-MB Quad SPI Flash, and several I/O devices. The clock used in the DIC is a 50-MHz frequency clock generated internally in the FPGA. Both the rise and fall edges of the clock have been used to detect the trigger instant. Therefore, the counter implemented in the FPGA increments the counts for T A and T AB every 10 ns. The detection of the trigger instant has been improved by programming the digital circuits proposed in [32]. The supply voltage of the pins in the FPGA is V DD = 3.3 V and V TL = 1.26 V approximately. These pins have been configured to be compatible with a CMOS-3.3 V standard, thus reducing I BA . The maximum value of this current has been determined experimentally and is, at most, 8 nA. Since during the discharging process I In = 43.96 µA, then (18) holds and (9) or (11) can be used for estimating C X . The selected OA is the TLV2475C by Texas Instruments, which has all the characteristics necessary to be included in the design and the  Table II shows these characteristics.
It is particularly noteworthy that the current going into the OA in the shutdown mode is about 450 nA, making it an excellent choice for low-power applications. On the other hand, Fig. 5 shows the test bench diagram used. The FPGA includes a control unit that controls and monitors the state of the pins to activate or deactivate a counter that provides the values T A and T B (in a number of clock cycles). This information is transferred to an arithmetic unit carrying out the C X calculations. The results are transferred using a UART port included in the FPGA to the FT2232HQ located in the CMOD-A7 and from there to a laptop.
Twenty-one discrete NP0 capacitors ranging from 100 pF to 96 nF (almost three orders of magnitude) were used for the measurements of C X . This wide range of values includes the operating ranges for many capacitive sensors. R In = 75 054 and R AB = 25 504 have been selected to meet the design considerations outlined in Section II. To establish the values of these elements, we used an LCR meter (Instek LCR-6300) with a basic accuracy of 0.05%. The value of R AB /R In is 0.34, while the right-hand side of (4) takes the value 0.62, thus ensuring the correct operation of the circuit. For R S , nine values have been chosen between 0 and 1.2 k in a logarithmic scale. With these selections, the lower time measurement is obtained for the lowest capacitance and R S = 1.2 k . In this case, T A ≈ 45 µs or a count of approximately 4500, and T A − T B ≈ 26 µs or a count of roughly 2600, meaning the effects of quantization are very much reduced. The T A0 − T B0 count is 80 in the offline autocalibration. Note that the influence of C off in (11) is negligible for values of C X greater than a few hundred picofarad, and in these cases, (9) can be used instead. Fig. 6 shows the actual waveforms of V A and V B in the circuit in Fig. 2 obtained in a Digilent Analog Discovery 2 data acquisition system when C X = 1.034 nF. The OA datasheet shows that T on = 5 µs, but we have programmed T on = 40 µs to visualize the signals better. T on = 10 µs and T ch = 10 µs have been set in regular circuit operation. It should be noted that the spurious values occurring in the signals during OA activation disappear when discharging starts. The effects would, therefore, only be appreciable at the beginning, meaning they do not affect (9), as mentioned previously.
A series of 100 estimations were made for each capacitor, and several figures of merit were used to analyze the results. The first one is the maximum relative error for the estimation  of C X , e R , which is given by where C X (i) is each of the estimations of C X using (11), and C X,a is the actual capacitance value. This error is shown in Fig. 7, where e R falls within a narrowband of 0.27%-0.77%. Errors are distributed uniformly along the X -axis. The slight increase in e R for lower capacitances is due, on the one hand, to the presence of stray capacitors since C off offsets many of the effects but does not entirely nullify them. On the other hand, with the choices made, u q is minimal but not 0. The errors are minor, considering they were obtained using an FPGA in a general-purpose circuit. Fig. 7 demonstrates, most importantly, that e R remains practically constant regardless of the value of R S (again excluding quantization effects). Systematic error, e S , is defined as Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.  where C is the average of all C X (i) and is generally considered the most crucial figure of merit for evaluating circuit error. In our case, the e S values obtained are shown in Fig. 8. Again, e S is practically constant and independent of R S , and its values are within a narrower 0.04%-0.37% band. Moreover, as e R and e S move in small value intervals, it would be logical to think that relative uncertainty in the estimation of C X will take a similar form. This behavior is observed in Fig. 9 since u(C X )/C X varies between 0.1% and 0.26%. This result confirms the validity of (22) in predicting a constant value of u(C X )/C X regardless of R S and C X . It also ensures that the relative uncertainties of the time measurements in (21) are also constant.
For comparison purposes, Fig. 10 shows these relative uncertainties together (for an intermediate value R S = 392 ). The data in the figure confirm practically constant results, with slightly noticeable quantization effects for lower capacitance capacitors. The remaining values of R S have demonstrated very similar behavior. Particularly worthy of note is that u(T A ) < u(T B ) for the entire range of C X . This phenomenon was already found in [31], which shows a DIC in which time measurement uncertainty is always higher in purely resistive nodes than in those connected to capacitors.
To check whether (11) corrects the effects of any differences in the values of V TL in P A and P B , the connections of these pins have been interchanged (P A is connected to V B and P B   to V A ). The maximum errors obtained in the original and new circuit configurations, together with the average errors in both configurations, e S , are shown in Table III for the maximum and minimum values of R S .
As can be seen in Table III, the differences between the two cases are minimal, if any.
The measurement time, T M , can be found in Fig. 3 as T M = T on + T ch + T A . Obviously, T M is maximum when C X = 96 nF and R S = 0. In this case, T M ≈ 4.5 ms. This is sufficient to monitor many physical and chemical processes, and this measurement time is much lower than would be required in impedanciometry.

IV. CONCLUSION
Parasitic series resistances can affect different capacitive sensors, distorting their capacitance estimation. Although there are some techniques to overcome this problem, such as classical impedanciometry, these require complicated hardware and can take a long time to provide the results.
DICs have few components and can take the advantage of the DPs to measure sensor magnitudes quickly and straightforwardly. However, to the best of our knowledge, there are no DICs capable of estimating a capacitive sensor's capacitance, C X , in the presence of parasitic series resistances. This article introduces a new DIC for this purpose.
The circuit requires just an OA, two resistors, and the DP. A single sensor charging-discharging process is carried out to obtain the estimate of C X , reducing power consumption and measurement time. Only two time measurements made by the DP during sensor discharging are necessary to calculate C X .
An FPGA as DP included in a general-purpose board has been used as the proof of concept. Although no specific hardware has been designed for the new circuit, systematic error is at most 0.37% for capacitors in the range 100 pF-96 nF (almost three orders of magnitude) with parasitic series resistances up to 1200 . Measurement time is only 4.5 ms in the worst case.