A MOS-Based Temperature Sensor With Inherent Inaccuracy Reduction Enabled by Time-Domain Operation

This article presents a MOS-based ON-chip temperature sensor system addressing both high-resolution and low-inaccuracy requirement, red while requiring a single temperature calibration point. Hence, the proposed temperature sensor system proves to be a low-cost solution, well addressing the requirements of the spreading market of system-on-chips (SoCs), mobile and wearable devices, and consumer electronics in general. The temperature sensor features a two-phase time-domain architecture, which employs as a sensing element a single NMOS transistor, biased alternatively with different currents, thus allowing achieving an inherent inaccuracy reduction. The proposed sensory system, fabricated in a standard 130-nm CMOS process, comprises, along the sensor core, a switched-capacitor analog interface circuit and a 1-bit second-order sigma-delta (<inline-formula> <tex-math notation="LaTeX">$\Sigma \Delta $ </tex-math></inline-formula>) analog-to-digital converter (ADC). The proposed temperature-to-digital converter (TDC), experimentally characterized considering a batch of 16 samples, achieves 40-mK resolution at 20-kHz switching frequency and +0.75/<inline-formula> <tex-math notation="LaTeX">$- 0.92\,\,^{\circ} \text{C}$ </tex-math></inline-formula> inaccuracy across the <inline-formula> <tex-math notation="LaTeX">$- 40\,\,^{\circ} \text{C}$ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">$90 ^{\circ} \text{C}$ </tex-math></inline-formula> temperature range after one-point calibration at room temperature, consuming <inline-formula> <tex-math notation="LaTeX">$25.4 \mu \text{W}$ </tex-math></inline-formula>, including the analog buffer added for testing purposes.


I. INTRODUCTION
I N THE last two decades, ON-chip temperature sensors have become of particular interest, thanks to the sharp increase in the market of mobile devices, system-on-chips (SoCs) and sensor networks, determined by the trend toward an increasingly connected and smart world. Indeed, ON-chip temperature sensors constitute a fundamental block in a wide range of applications [1] as they can be used for realizing precise relative measurements, which require high resolution, or for implementing reliable absolute measurements, which necessitate low inaccuracy. Precise relative temperature measurements are Manuscript  needed in micro-electro-mechanical systems (MEMS) to compensate for the thermal drift of their parameters, which would otherwise determine a degradation in their performance [2], [3], [4], [5], while reliable absolute temperature measurements are required in biomedical applications [6], [7], [8], e.g., for implementing the reference detectors in contactless temperature sensors for the human body [9], and in thermal monitoring of the food and healthcare products cold chain maintenance [10], [11], [12]. Moreover, ON-chip temperature sensors are a fundamental block in microprocessors thermal management, as they enable responsive temperature tracking in order to allow dynamic voltage and frequency scaling (DVFS) and the cooling fans speed regulation [13], [14], [15], as well as in bandgap reference generation [16], [17]. Depending on the specific application, therefore, resolution or inaccuracy can be the most critical characteristic of the temperature sensor system. However, regardless of the targeted application, in order to be successfully suited for the consumer market, the ON-chip temperature sensor must be low cost. One of the most significant impacts on the temperature sensor system cost is the required calibration procedure, as each calibration point involves maintaining the sensor system chip at a fixed and controlled temperature. This process is quite expensive as heating/cooling of the temperature sensor chip is time-consuming and requires employing dedicated instrumentation (e.g., climatic chamber). For this reason, one-point calibration devices are significantly cheaper than the ones requiring two calibration points.
Typical temperature sensor systems are implemented relying on passive ON-chip components (i.e., resistors and capacitors), BJT or MOS devices as sensing elements. Systems relying on passive ON-chip components employ standard [18] and switched-capacitor [19] Wheatstone bridge structures, Vienna bridge configurations [20] or RC networks [21]. They can work with very low supply voltages, however they may occupy significant silicon area and can be more prone to process and mismatch variations, thus typically requiring two calibration points. BJT-based temperature sensors, which constitute the most traditional approach, are implemented by considering the voltage difference between two BJT devices, differing in size and/or biasing current [5], [22], [23], [24]. They feature high accuracy but are not compatible with sub-1 V supply voltages, as they are limited by the BJT base-emitter voltage. This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ BJT devices my occupy a larger area with respect to MOS devices; furthermore, not in every CMOS process good BJTs can be obtained, as they are usually parasitic devices. MOS devices are mostly employed for realizing sensor structures that rely on the temperature dependence of delay lines and oscillators [25], [26], [27], [28]. The temperature dependence in those cases, however, is highly nonlinear and necessitates at least two temperature calibration points.
This article tackles the requirements of the consumer market by proposing a versatile architecture that can be employed in different applications, as it addresses both high resolution (<50 mK) and low relative inaccuracy (Rel IA) (<2%) specifications, while simultaneously featuring low cost since it achieves good inaccuracy performance with a single temperature calibration point. Indeed, the proposed system, thanks to its two-phase time-domain operation, aims at reducing inaccuracy by employing a single MOS device as the sensing element, thus avoiding the mismatch effects due to the sensing element itself. The employed MOS device is alternatively biased with different currents in the two operating phases, then implementing the difference operation to obtain the temperature-dependent voltage signal in time domain. The proposed sensor system comprises the sensor core, an analog interface to provide gain and a 1-bit second-order analog-to-digital converter (ADC), which converts the temperature into a digital signal. Moreover, a sampler and an analog buffer are added for enabling separate testing of the analog interface. The overall system, fabricated in a standard 130-nm CMOS process, features, considering a 20-kHz switching frequency, 25.4-µW power consumption, 40-mK resolution and 1.7% Rel IA across the consumer application temperature range after one-point calibration at room temperature.
The article is organized as follows. Section II illustrates the proposed temperature sensor system, describing the different blocks of implementation and operation and motivating the design choices, Section III reports the measurement results, characterizing both the analog interface and the overall system, and Section IV concludes the article.

II. PROPOSED TEMPERATURE SENSOR SYSTEM
The proposed temperature sensor system block diagram is illustrated in Fig. 1: it features the sensor core, the analog interface, the ADC, and the sampler and analog buffer, added for testing purposes, which allow measuring directly the analog interface output voltage. The circuit operation is controlled by complementary and nonoverlapping signals φ 1 and φ 2 , derived from a clock with period T and duty-cycle D, which determine two phases of operation, Phase 1 and Phase 2, when φ 1 and φ 2 , respectively, are high. Control signal φ S , derived from a clock with period T and duty-cycle D S , allows sampling of the analog interface output in order to reconstruct it at dc.
The sensor core is implemented through a two-phase architecture, employing a single diode-connected NMOS transistor, M S , operating in the subthreshold region, alternatively biased with current I 1 = (a + b) · I B or I 2 = b · I B depending on the respective switching phase. Hence, the sensor core originates a square wave at node V out1 , going from V out,φ2 to V out,φ1 , where V out,φi is the M S transistor gate-to-source voltage when the control signal φ i is high. The signal of interest, V out = V out,φ1 −V out,φ2 , is then processed by the analog interface, which provides gain and a negative voltage shift, in order to maintain the amplified signal within the analog interface dynamic range. The analog interface output signal, found at note V out2 , consisting of a square wave between the common mode voltage, V CM , and the amplified and shifted version of V out , V ′ out,φ2 , is then processed by the second-order ADC, which again provides gain as well as a positive voltage shift, while converting signal V ′ out , i.e., the amplitude of the square wave found at the analog interface output, to the digital domain. The analog interface output is sampled according to φ S in order to reconstruct the dc signal and measure directly the analog output voltage through a buffer: indeed the sampling occurs during a sub-interval of Phase 2, determined by D S , so that the settling after the transition is finished and only the output signal of interest is sampled (during Phase 1 the analog interface output is substantially equal to V CM ).
Since the ADC block implements a subtraction operation (as the ADC input square wave amplitude is the one converted to a digital signal) while providing gain and a voltage shift, the analog interface may be redundant, provided that the selected overall gain factor is sufficiently low so that the amplified signal does not exceed the ADC output range. However, if extra gain is required, the analog interface block becomes necessary, as it implements a negative voltage shift (whereas the voltage shift given by the ADC is positive), which allows maintaining the output signal within the ADC range. The fabricated circuit includes the analog interface in order to evaluate the overall system.

A. Sensor Core
The sensor core circuit is schematically illustrated in Fig. 2. Provided that the drain-to-source voltage is larger than a few (kT /q) (i.e., the thermal voltage), the M S gate-to-source  voltage during Phase i is given by where V TH is the transistor threshold voltage, k is the Boltzmann's constant, T is the temperature, q the magnitude of the electron charge, n a process-dependent parameter, I i the biasing current in Phase i and I D0 is the drain-to-substrate leakage current times the transistor aspect ratio. This yields an amplitude of the voltage square wave found at node V out1 equal to where I 1 and I 2 are the sensing element bias currents in Phase 1 and Phase 2, respectively. Hence, the voltage V out features a proportional-to-absolute-temperature (PTAT) behavior, resulting in sensitivity to temperature equal to Therefore, the larger the bias current ratio is, the higher the sensitivity value. However, choosing I 2 too small would result in increased mismatch effects and keeping a very large bias current ratio while maintaining I 2 sufficiently large would yield significant power consumption. For these reasons, a bias current ratio equal to 0.1 is chosen, implemented by adopting mirroring factors equal to 0.9 and 0.1 with respect to I MOS for I 1 and I 2 , respectively. In order to size M S , sensitivity, signal-to-noise ratio (SNR) and settling time must be taken into consideration. Indeed, although the sensitivity is determined at first order by the bias currents ratio, second-order effects also take place modifying it. Moreover, to minimize the system conversion time, period T and duty-cycle D should be chosen so that D · T is approximately equal to the overall system settling time, found at node V out2 , which is determined by both the analog interface bandwidth and the settling time at node V out1 . The time behavior at node V out1 can be modeled as resulting from the low pass action of an equivalent RC circuit where C is given by the input capacitance of the analog interface plus the parasitic capacitances between node V out1 and ground (mainly the gate-to-source, drain-to-source, gate-to-bulk, and drainto-bulk capacitances of M S ), while the R is given by 1/g m (where g m is the transconductance of transistor M S ), as that is significantly smaller than the drain-to-source resistances of the current mirror transistors. As M S operates in the subthreshold region, and therefore its transconductance is directly proportional to its bias current, 1/g m varies depending on the switching phase and the corresponding bias current: hence, when the bias current switches from I 1 to I 2 and vice versa, the resistance varies, thus resulting in different values for the rise time and the fall time. Being larger than the rise time, the fall time, t f , is considered for determining the settling time, t s , as Since the equivalent resistance varies during the switching operation itself, the circuit does not behave as a true RC circuit, however, the model is sufficient for making a sensible settling time estimation. In order to determine the optimal aspect ratio, W/L, for M S , the sensor core was simulated in Cadence Virtuoso considering the same M S area and I MOS bias current while varying the transistor aspect ratio: the obtained sensitivity, SNR and settling time values for V out are reported in Fig. 3. The simulation results were obtained considering a 720-µm 2 M S area and 4-µA I MOS current, however, curves with similar trends are found with different area and current constraints: hence, in order to achieve the best tradeoff between sensitivity, SNR and settling time, an aspect ratio equal to 20 was selected.
For selecting the optimal sensing element area, once its aspect ratio was fixed, the sensor core was simulated in Cadence Virtuoso for different M S area values: its performance considering sensitivity, SNR, and settling time is illustrated in Fig. 4. A sensing element area equal to 720 µm 2 (six fingers with 20-µm width and 6-µm length) was chosen.

B. Analog Interface Circuit
The square wave signal at the sensor core output is processed by the analog interface circuit illustrated in Fig. 5, which consists of a switched capacitor amplifier, controlled by signals φ 1 and φ 2 , employing the autozero technique for removing the amplifier offset.
Considering the overall charge across capacitors C A , C F , and C X during Phase 1 (when φ 1 is high) and the one during Phase 2 (when φ 2 is high) and by equating (5) and (6) applying the charge conservation principle, it is found that where V out = V out,φ1 − V out,φ2 is the amplitude of the square wave found at V out1 and V ′ out,φ2 is the voltage found at V out2 during Phase 2 (during Phase 1 the voltage is equal to V CM ). Hence, the structure performs the difference operation between the voltages found at V out1 during the two different operating phases, then amplifying the resulting V out voltage by a factor k A = (C A /C F ) and shifting it by −k X · V CM where k X = (C X /C F ): the voltage found at node V out2 , therefore, is a square wave ranging from V CM to k A · V out − k X · V CM .
In this design C A = 17 · C F and C X = C F , with C F equal to 500 fF, yielding k A = 17 and k X = 1. The operational amplifier is implemented through the mirrored architecture reported in Fig. 6. In order to maximize the closed-loop amplifier bandwidth, the compensation capacitance was split in two, with the 6.5-pF capacitance connected to the output only during Phase 2, when φ 1 is high and φ 2 is low: indeed the overall 7-pF capacitance is required for ensuring stability only when the operational amplifier is closed in the unity gain feedback configuration; when the gain determined by the feedback is (C A /C F ) = 17, a smaller capacitance suffices for implementing the compensation, as shown in Fig. 7, which reports the Bode diagrams simulated in Cadence Virtuoso.
A sample and hold and an analog buffer, implemented with the same mirrored structure as the switched capacitor amplifier, are added for testing purposes in order to reconstruct the V ′ out,φ2 signal at dc and directly measure it.

C. ADC
The analog interface output is processed by the 1-bit secondorder ADC reported in Fig. 8, which converts the square wave amplitude, V ′ out , found at the analog interface output node V out2 . The ADC is implemented by a switched capacitor architecture, controlled by φ 1 and φ 2 , which provides gain and a positive voltage shift, along with performing the conversion to the digital domain: indeed, the converted voltage is k B · V ′ out + V S , where k B is equal to (C B /C) and V S is provided, along with the converter reference voltages, V refP and V refN , through a buffer. In the proposed design C B = C = 200 fF, resulting in k B equal to 1, and V S = V CM . Indeed it was preferred to provide the gain with the analog interface block, as it also implements the negative voltage shift which allows maintaining the output voltage within the system dynamic range. V S is chosen equal to the common mode voltage as that permits to cancel out the −V CM term in V ′ out = V ′ out,φ2 − V CM , thus directly converting the analog output V ′ out,φ2 = k A · V out − k X · V CM . The same mirrored structure employed for the analog interface amplifier is adopted for the integrators, whose feedback networks implement 0.5 coefficients, and for the buffers. A latched comparator, whose structure is detailed in Fig. 9 where latch = φ 1 and latchN = φ 2 , implements the single bit quantizer. The comparator shares the same biasing circuit of the operational amplifiers.

D. Design Tradeoffs: Speed, Power Consumption and SNR
The tradeoffs concerning the sizing of the NMOS acting as the sensing element have been discussed in Section II-A; however, in order to optimally design the overall system, the relation between the total power consumption and the settling time, determining the minimum switching period, must be taken into account. For optimizing the system performance, the energy per conversion (i.e., the product of power consumption and conversion time) must be minimized: as the conversion time is directly dependent on the settling time and minimum period, the design approach is minimizing the product between power consumption and minimum period. The minimum period is derived as the ratio between the settling time and the duty cycle D. Lowering the duty cycle allows reducing the power consumption, however, it also results in larger minimum period requirements: hence, the best compromise in terms of energy per conversion is selecting D equal to 0.5. In order to precisely estimate the overall system settling time,  the sensitivity value found at the analog interface output was studied as a function of the period, adopting a duty cycle equal to 0.5, for various combinations of sensor core bias current (I MOS ) and mirrored amplifier bias current (I AMP ). The sensitivity value was normalized to the maximum sensitivity, obtained once the settling is achieved; the minimum period was then identified as the one ensuring a normalized sensitivity equal to 0.99. The simulated normalized sensitivity as a function of the period considering I MOS = 4 µA and I AMP = 0.5 µA is reported as an example in Fig. 10, yielding a 50-µs minimum period. The minimum period for several I MOS -I AMP combinations was derived, starting from Cadence Virtuoso simulations, with the described procedure and a figure-ofmerit, FoM TP , was defined as the product between the obtained minimum period and the power consumption (excluding the buffers): the bias current values ensuring the lowest FoM TP are the ones minimizing the energy per conversion. The plot of FoM TP as a function of both the minimum period and the power consumption is illustrated in Fig. 11: the minimum point corresponds to I MOS and I AMP equal to 2 and 0.5 µA respectively. The energy per conversion, however, is not the only parameter of interest: indeed also the SNR must be taken into account. The simulated SNR of the sensor core as a function of I MOS is reported in Fig. 12. In order to achieve good SNR while maintaining low energy per conversion, I AMP and I MOS equal respectively to 0.5 and 4 µA are selected for the design, as that allows obtaining a sensor core SNR with a 26.5% improvement with respect to the case with I MOS = 2 µA, while facing a worsening of 16.6% in FoM TP .

E. Inherent Inaccuracy Reduction
In order to quantify the inherent inaccuracy reduction due to the employed single-MOS time-domain architecture, Monte Carlo simulations, including both process and mismatch variations, were carried out in Cadence Virtuoso for the sensor core and the analog interface, considering the proposed structure and a standard sensor core architecture employing two separate NMOS devices. In order to make a fair comparison, the NMOS transistors in the standard structure were sized as the one in the proposed architecture and the two currents employed for biasing the transistors were set equal to the current biasing the time-domain architecture in Phase 1 and Phase 2, respectively. The simulated standard deviation results considering the analog interface output sensitivity and voltage at room temperature are reported in Table I. The employed single-MOS time-domain architecture allows reducing the sensitivity spread, and therefore the inaccuracy, of 10% with respect to the standard sensor core structure.

III. MEASUREMENT RESULTS
The proposed temperature sensor system was fabricated in a standard 130-nm CMOS process. The chip micrograph is shown in Fig. 13. The total test-chip core area is 0.63 mm 2 , including the reference and analog buffers.  The proposed system performance was verified experimentally considering a batch of 16 samples, taken from the same wafer lot. Along with the overall system, characterized through the digital output acquisition, also the analog interface was tested as a stand-alone by measuring the analog buffer output. The measurement setup, controlled by means of a LabVIEW program, is illustrated in Fig. 14: two Agilent E3631A power supplies were employed for providing the reference and supply voltages, a Tektronix AFG3252 function generator supplied the clock signals, a Keithley 2000 multimeter acquired the analog output, while the digital output data were gathered with a Digilent Digital Discovery working as a logic analyzer. The Keithley 2000 digital multimeter used in ammeter mode was also employed for measuring power consumption. The fabricated circuits were tested in a climatic chamber (ACS-DY(T) model), with a controlled ambient temperature ranging between −40 • C and 90 • C, monitored directly by the climatic chamber temperature sensor. MATLAB software was employed for processing the acquired measurement data. The supply voltage, V DD , was set to 1.8 V, V CM to 0.9 V, V refP to 1.4 V, V refN to 0.4 V and V S to 0.9 V. The sensor core bias current, I MOS , and the amplifier bias current, I AMP , were adjusted to 4 and 0.5 µA, respectively, by means of on-board trimming resistors.
The measured analog buffer output and ADC digital output, converted back to voltage, are reported in Fig. 15. A 1-kHz switching frequency and duty cycles D and D S equal to 0.15 and 0.5, respectively, were employed for the analog buffer output measurements; for the ADC output acquisition, instead, a 20-kHz switching frequency, corresponding to the minimum employable period, duty cycles D and D S equal to 0.5 and 2 16 averaged samples were considered. The analog buffer    Table II. The ADC circuit substantially does not contribute in terms of inaccuracy and linearity, as it can also be deduced from the regression index between the analog and overall system output, defined as where σ err is the standard deviation of the difference between the ADC output and the analog buffer output and σ ADC Out is the standard deviation of the population given by the ADC output from −40 • C to 90 • C. Indeed as the regression index is 0.99971, the analog-to-digital conversion is performed almost ideally.
The overall system, therefore, is fully characterized considering measurement results acquired at the ADC output, considering 0.5 duty cycles and 20-kHz switching frequency. The measured bitstream power spectral density (PSD), expressed in temperature, as a function of the frequency, is reported in Fig. 16: the noise shaping effect of the secondorder ADC is clearly visible. The PSD was obtained considering 2 16 samples at room temperature, processed with a Hanning window, and removing the average (i.e., the dc component).
The resolution as a function of the conversion time, after performing in MATLAB a decimation with an eighth-order Chebyshev filter, is plotted in Fig. 17: a conversion time equal to 6.4 ms, corresponding to an oversampling factor equal to 128, was selected as it ensures the best tradeoff between energy-per-conversion and resolution.
The system inaccuracy after one-point digital calibration at room temperature, measured for the selected conversion time across the 16-samples batch, is illustrated in Fig. 18: a worst case +0.75 • C/−0.92 • C is achieved, corresponding approximately to a 1.7 • C peak-to-peak inaccuracy (PP IA) and a 1.3% Rel IA, considering the consumer application temperature range, i.e., from −40 • C to 90 • C. The inaccuracy was calculated as follows. First of all, in order to implement the digital one-point calibration, the converted ADC output voltage values, measured for each sample at 30 • C (V out, @30 • C, n ), were averaged, as illustrated by (9), and the difference between the obtained averaged value and the nth sample measurement at the same temperature was derived, thus obtaining the offset correction used for the calibration, as indicated by (10) Offset n = V out, @30 • C, n − V out, @30 • C, n .
The offset was added to the measured output voltage versus temperature characteristic of each sample, thus shifting each of the curves reported in Fig. 15. The shifted converted ADC output versus temperature curves were then fit, resulting, for each sample, in a third-order polynomial function, which provides the output voltage depending on temperature. A thirdorder polynomial was selected instead of a perfectly linear function, in order to account for the nonlinearity effects, albeit very small, of the converted ADC output versus temperature curve. Each polynomial was then inverted with MATLAB, thus obtaining functions that issue the temperature corresponding to the measured converted ADC output voltage for the specific sample. In this way, by providing the sample converted ADC output voltage V out,x as input for the derived function, the corresponding temperature T x is calculated. The temperatures at which the measurements were performed were controlled by means of the climatic chamber and therefore known. The difference between the controlled climatic chamber temperature, T Real , (i.e., the "real" temperature value) and the one derived from the inverted function specific to each sample, T x , (i.e., the value measured by the proposed sensor system) was calculated for each measured temperature value, thus yielding a temperature error (i.e., inaccuracy) curve for each sample Those curves are the ones illustrated in Fig. 18. The difference between the maximum error value (positive) and the minimum error value (negative) for each considered temperature is then taken into account. The worst case (larger) difference is the peak-to-peak inaccuracy. The Rel IA is instead derived as the peak-to-peak inaccuracy divided by the temperature range. The power breakdown of the fabricated temperature sensor system is illustrated schematically in Fig. 19(a). The analog output buffer is added only for testing purposes, hence its power consumption, which is comparable to the one of the analog interface, is not significant; the reference buffers, however, are an integral part of the design and in this realization they burn a notable fraction of the overall power. This is due to the fact that in this first realization, for ease and speed of design, as the focus of the work was more on the time-domain sensor core, the buffers are not optimized: indeed they share the same structure and bias current of the analog interface amplifier and ADC integrators. In particular, the power consumption would be significantly lowered simply by decreasing the value of their biasing current, which would be achieved by employing a scaled-down version of I AMP . The overall system was simulated in Cadence Virtuoso duplicating the bias circuit, selecting I AMP = 50 nA, in order to have a dedicated bias circuit for the reference buffers: the performance, as expected, does not change since the bias current reduction translates to a lowering of the buffers bandwidth, which does not have any significant effect as the buffer input is a dc voltage. The power breakdown considering the simulation results for the scaled down buffer bias current case is reported in Fig. 19(b). Moreover, for applications where the power consumption is a strong concern, the ADC could be directly cascaded to the sensor core, provided that the achievable gain is sufficient, thus removing the analog interface circuit.
The measured performance of the proposed temperature sensor system is summarized and compared to other stateof-the-art MOS-based temperature sensors in Table III. The proposed system achieves the third best resolution value and excellent performance in terms of inaccuracy, at the cost of a larger area and resolution figure-of-merit (Res FoM). However, the area and the power consumption could be lowered by optimizing the reference buffers design. The reported inaccuracy is obtained after a one-point temperature calibration at room temperature, outperforming other sensors with the same number of trimming points. Indeed, better inaccuracy values are achieved only by works requiring two temperature trimming points, which entail a significant increase in the calibration costs. Moreover the proposed temperature sensor system outperforms also few works with more than one calibration point, thus proving to be a low-cost but performing solution.

IV. CONCLUSION
This article has proposed a MOS-based temperature sensor operating in time-domain, which employs a single NMOS transistor as the sensing element, thus achieving an inherent inaccuracy reduction. The fabricated sensor, integrated into a Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. standard 130-nm CMOS process, comprises the sensor core, the analog interface circuit, the 1-bit second-order ADC and an analog buffer added for testing purposes. The proposed sensory system has been extensively measured, characterizing both the analog interface and the overall sensor performance. A peak-to-peak inaccuracy equal to 1.7 • C, corresponding to 1.3% Rel IA, was measured across a 16-samples batch, considering the −40 • C-90 • C temperature range and one-point calibration at 30 • C, thus outperforming other state-of-the-art MOS-based sensors employing the same number of trimming points. The proposed sensor also features 40-mK resolution, when optimizing the energy-per-conversion/resolution tradeoff, thus making the system suitable for realizing precise relative measurements, as well as for implementing reliable absolute measurements, while simultaneously featuring low cost thanks to the single calibration point required.
Elisabetta Moisello (Member, IEEE) was born in Pavia, Italy, in 1993. She received the master's degree (summa cum laude) in electronic engineering and the Ph.D. degree in microelectronics from the University of Pavia, Pavia, in 2017 and 2020, respectively.
She is currently a Post-Doctoral Research Fellow and a Contract Professor with the University of Pavia. Her research interests include sensor interface circuits, integrated temperature to digital converters, switching dc-dc converters, and wireless power transfer.