Passive Component Optimization for Current-Source-Inverters

In addition to the actual semiconductor components and the cooling solutions required to dissipate losses, passive components account for a large part of the volume of power electronic converters. This publication presents methods for optimizing the volume or occupied PCB board area of the passive components of current source inverters (CSIs). For this converter topology, these are primarily composed of the filter capacitors placed on the output terminals and the DC-link inductance acting as the main energy storage device in the DC-link. Design equations for the design of these components are presented first. In addition to the basic relationships for determining the capacitance or inductance of the respective components, other constraints for their design are also taken into account. Furthermore, an optimization process is given for both the filter capacitors and the DC-link inductance, with which the volume or the occupied board area of the respective components can be designed as small as possible. On the basis of the optimization results for various input parameters, analytical relationships are then determined that can be used to quickly and easily estimate the volume and area at the beginning of a converter design process.


Passive Component Optimization for
Current-Source-Inverters

Benedikt Riegler , Graduate Student Member, IEEE, and Annette Muetze
Abstract-In addition to the actual semiconductor components and the cooling solutions required to dissipate losses, passive components account for a large part of the volume of power electronic converters.This publication presents methods for optimizing the volume or occupied PCB board area of the passive components of current source inverters (CSIs).For this converter topology, these are primarily composed of the filter capacitors placed on the output terminals and the DC-link inductance acting as the main energy storage device in the DC-link.Design equations for the design of these components are presented first.In addition to the basic relationships for determining the capacitance or inductance of the respective components, other constraints for their design are also taken into account.Furthermore, an optimization process is given for both the filter capacitors and the DC-link inductance, with which the volume or the occupied board area of the respective components can be designed as small as possible.On the basis of the optimization results for various input parameters, analytical relationships are then determined that can be used to quickly and easily estimate the volume and area at the beginning of a converter design process.Index Terms-Capacitors, converters, inductors, optimization, pulse width modulation converters.

I. INTRODUCTION
T HE development of SiC and GaN-based WBG semicon- ductor switches enables power electronic converters for variable speed drives (VSDs) and applications in power grids to operate at much higher switching frequencies than previously possible with conventional silicon (Si) based IGBTs and MOSFETs.Additionally, these new devices offer lower on-state resistance and thus lower conduction losses for the same chip size and, in the case of SiC, are better suited for operation at high temperatures (>150 • C) [2].However, increasing the switching frequency of the commonly used voltage-source-converters (VSCs) and therefore the dv dt of the pulse width modulated output voltages not only offers advantages, such as a potential reduction Fig. 1.Basic circuit diagram of the inverter side of a current source converter (current-source-inverter, CSI).The rectifier side is replaced with a controllable voltage source that aims to keep the DC-link current constant on average.Here, the reverse-blocking semiconductor switches are constructed from MOSFETs and diodes.
of the size of passive energy storage components or filters used, but also leads to new challenges and risks [3], [4], [5].These challenges caused by steep converter output voltage slopes can include, but are not limited to: r Terminal overvoltages at the VSD if the converter and drive are connected by a long cable and there is a characteristic impedance mismatch between the two systems [4], [5], [6].These can significantly stress or even damage the drive's insulation system.r Emission of high-frequency electromagnetic disturbances violating electromagnetic compatibility standards [3].
r Increase in harmonic motor losses due to high-frequency output voltage components [7].One way to address these problems is to use the increasingly popular current-source converter (CSC, see Fig. 1) topology [4], [8], [9], [10] instead of a VSC.In this case, an inductor is used as the main energy storage device in the DC-link which aims to maintain a constant average DC-link current while capacitors at the output provide an alternative current path for switching inductive loads.These components together possess the characteristic of a second-order filter which allows the generation of continuous rather than switched output voltages.In addition, this topology offers the potential of operation at high temperatures, since the CSC's passive components are usually much more temperature resistant than those of the VSC [4].
However, one major disadvantage of the CSC is that reverseblocking (RB) or bidirectional (BD) switches have to be used for the main switching elements.To realize RB switches with This work is licensed under a Creative Commons Attribution 4.0 License.For more information, see https://creativecommons.org/licenses/by/4.0/Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.available components, a conventional reverse conducting switch can be combined with a diode in series, which increases the circuit losses due to the forward voltage and reverse-recovery effect, or another antiserial switch.Fig. 2 depicts the circuit symbols of the different RB switch variants based on WBG technology such as SiC MOSFETs, GaN HEMTs, or SiC Schottky barrier diodes (SBDs).The symbol presented in Fig. 2(e) represents a dual-gate monolithic BD GaN HEMT that is promising for use in CSCs [9], [11], [12], [13], [14], [15].However, these are still in the development phase and are not yet commercially available.

II. CONTRIBUTION
This article improves and extends the findings from [1], which presents a volume comparison of the passive components of the inverter side of CSC and VSC (current-source-inverter CSI and voltage-source-inverter VSI).There, in the first step, analytic relationships for the design of the components were derived.Then, based on the determined quantities, the volume of the passive components of a CSI and a VSI with a sinusoidal output filter is calculated, which can provide a three-phase line-to-line output voltage of 400 V at an output current of 10.6 A (7.3 kW).
In this article, the design process of the passive components of the CSI is explained in more detail and more general relationships between the basic design parameters like the maximum output voltage or current and the passive component volume are derived.For this purpose, the analytic design of the passive components is first revisited in Section III where Section II-I-A describes the underlying space vector modulation (SVM) concept.
As regards the dimensioning of the filter capacitors, a few studies have already been carried out on this subject.[16] provides the basis for calculating the capacitance, but only the harmonic content of the output voltages is derived and no formulae for the capacitaces are given.In [17] and [18], on the other hand, an equation for the filter capacitors is given directly, but there is no derivation and the remaining constraints of the filter capacitors, such as the maximum permissible voltage and RMS current, are not dealt with.Therefore, in Section III-B, a detailed dimensioning process of the filter capacitors is presented, taking into account not only their capacitance but also other constraints.
Several methods have been described in the literature for the design of the DC-link inductor, all of which give similar results.However, [17], [18], [19], [20] each only describe a formula for the inductance of the DC-link inductor, which does not take into account the other constraints of the design such as the RMS current and the maximum current with respect to saturation.In Section III-C, therefore, a detailed derivation of the necessary parameters for the DC-link inductance is presented in order to be able to easily adapt them to newly developed control and modulation schemes.
In Section IV the design and selection process for minimizing volume and occupied board area of the filter capacitors is shown, where, in contrast to [1], the dielectric is considered in greater depth and the parallel and series connection of commercially available components is taken into account.For the physical design of the DC-link inductance in Section V, the method from [1], which is based on [21] is described in further detail.It is extended by a better approximation of the winding geometry and takes into account the additional volume of the outer layers of the winding and adds it to the total volume of the device.In addition, the approximation of losses is improved by better modelling of the inductor current waveform and a wider range of available core materials is considered for optimisation.Section VI recapitulates the obtained results and highlights the relationships of the volume of the respective passive components in relation to various fundamental design parameters (e.g., system power, output voltage harmonic content,...) of the CSI.The results are then summarized in Section VII.

III. DESIGN OF THE CSI'S PASSIVE COMPONENTS
This section describes the design process for the passive components of the CSI, the DC-link inductor, and the filter capacitors.For this purpose, the space vector modulation strategy for the inverter is first explained, on the basis of which the following calculations are carried out.The parameters required to properly select the filter capacitors include the capacitance of the filter capacitors C f , the maximum tolerable peak-to-peak value of the capacitor voltage ripple Δv C max , the maximum RMS current I C max through and the maximum occurring voltage across the filter capacitors v C max .For the DC-link inductor, the parameters are the inductance of the DC-link inductor L dc , the maximum tolerable peak-to-peak value of the inductor current ripple Δi dc max as well as the maximum inductor RMS current I dc max and, regarding saturation, the peak value of the current i dc max .

A. Space Vector Modulation
Fig. 1 portrays the simplified circuit model of the CSI circuit.The rectifier on the input side is replaced by a controllable voltage source since this publication only covers the inverter part of the circuit, which consists of a rectifier stage as well.It is assumed that in steady-state operation this voltage source always outputs the voltage v dc necessary to keep the average value of the DC-link current i dc at the value selected in the design process.The semiconductor switches are modeled by ideal reverse-blocking switches.The filter capacitors C f placed between the load and the outputs of the semiconductor stage are responsible for providing an alternative current path in case of an inductive load where overvoltages would occur if the current Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Fig. 3. Space vector diagram for the CSI with 6 active (V 1 ...V 6 ) and three zero space vectors (V 7 ...V 9 ) dividing the complex plane into a hexagon with six sectors (I...VI).Here, the reference space vector m is located in sector I.
carrying DC-link inductor is connected in series to the load at any switching transition.
In the model presented herein, it is assumed that the states of the switches S 1 to S 6 are calculated via sinusoidal space vector modulation with modulation strategy "Mod 1" according to [16].This strategy offers the lowest switching losses of all strategies with constant DC-link current, because only three commutation processes are carried out per PWM period.The corresponding space vector diagram with the active space vectors V 1 to V 6 and the zero states V 7 to V 9 in complex vector representation is shown in Fig. 3. Assuming a constant DC-link current I dc = i dc , the three-phase current flowing from the switch nodes can be calculated in complex vector representation i S for the respective switching state by multiplying this DC-link current by one of the specified vectors.
To output an arbitrary complex space vector m = M • e j ϕ m with maximum length M max = 1, first the sector (I ...VI) in which m is located is determined.Subsequently, within a constant time period T pwm = 1 f pwm , the adjacent space vectors bounding the computed sector, as well as an arbitrarily selectable zero space vector, are applied in a time-weighted way (linearlycombined).In contrast to the VSI, the choice of the zero space vector does not influence the voltage or current ripple in the filter capacitors and the DC-link inductance [16].However, it is possible to optimize the number of switching actions per period through proper selection.The three space vectors, as well as the time intervals with which these are weighted, are specified after the determination of the sector with V x and t x (adjacent space vector in counterclockwise direction) with V y and t y (adjacent space vector in clockwise direction) and with V 0 and t 0 (arbitrary zero space vector).For example, if m is located in sector I, V x = V 1 , and V y = V 6 .The time intervals for the weighting can then be calculated by (1).

B. Parameters of the Filter Capacitors
Assuming that the complex load current space vector i is constant over the time duration of a switching period, the current into the filter capacitors i C can be calculated via the corresponding KCL, i C = i S − i, for one time interval where the switch position does not change.
It is assumed that the load current space vector corresponds to the average value of the output current over the course of a switching period, i = m • I dc .The change in the output voltage space vector v during a time interval can then be calculated by substituting the capacitor current into the component equation for the capacitor.The resulting transformed difference equations are shown in (2) for the respective time intervals.
This equation can then be further evaluated for each sector and, to obtain the change in phase voltage, be transformed back from the complex space vector representation to phase quantities.To compute the output voltage's peak-to-peak value in phase a, Δv a , the resulting equations are analyzed.Δv a can therefore be calculated independently of the sector via (3) [16].
Fig. 4 shows the analytically calculated value for Δv a (ϕ m ) for different values of M while Fig. 5 shows one period of the simulated output voltage waveform of phase a v a .The simulation was performed in MATLAB/Simulink, assuming ideal switches for the semiconductor devices.The average DC-link current was chosen to be i dc = 15 A, the modulation index was M = 1, the PWM switching frequency f pwm = 100 kHz, the filter capacitances C f = 1 μF and the ohmic load was set to provide a line-to-line output voltage of 400 V at this operating Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.point.The additional envelope curve plotted in Fig. 5 was calculated analytically using (2).It can be observed that the analytical computation of the voltage ripple agrees excellently with the simulated values.Any deviations are due to the ripple of the DC-link current, which is neglected in the analytic derivation.
To obtain a correlation for the choice of filter capacitors based on the maximum tolerable output voltage ripple Δv max , ( 2) is analyzed and converted to C f .
It should be noted, that Δv max is independent of the power factor of the load and can be found at M ∈ [ 1 2 , 1].Additionally, with the help of the presented derivations, the maximum voltage occurring at the capacitors v C max can also be estimated.This occurs when the peak value of the voltage ripple and, due to a power factor cos(ϕ) = 1 of the load, the peak value of the fundamental wave coincide.v C max can be computed using (5).
To compute the RMS current through each of the filter capacitors I C during operation, the RMS value of the sinusoidal output current I is subtracted quadratically from the RMS current at the switch nodes I S given in [16] resulting in (6).The maximum value I C max appears at M = 2 π and can be computed by (7).

C. Parameters of the DC-Link Inductor
The peak-to-peak value of the DC-link current Δi dc is calculated in a similar way.It is now assumed that instead of i dc the circuit's complex output voltage v = √ 2 M V ac e jϕ v is constant during one switching period.Here, V ac describes the maximum .
RMS value of the phase voltages at the inverter output (occurs at M = 1 but is load dependent) and ϕ v the phase shift between the fundamental waveform of output current (reference signal) and output voltage.The DC-voltage source modeling the rectifier must therefore provide the voltage to maintain the circuit's power balance in steady-state operation and thus keep the average value of the DC-link current constant.For the following calculation, the output voltage v can no longer be considered a complex vector and has to be split into it's three-phase fundamental waveform components.
In addition, the switch positions of S 1 to S 6 have to be taken into account.Using the time intervals calculated by (1) for a reference space vector in sector I, t xI , t yI and, t 0I , the change in current during each interval through the DC-link inductance can be computed using the difference equation shown in (9).
The peak-to-peak value of the DC-link current Δi dc is the maximum value of the current change of the three intervals and depends on the parameters ϕ vi , ϕ m , and M .Further evaluation of (9) for all sectors reveals that Δi dc is periodic with respect to π 3 .Fig. 6 shows the analytically calculated value for Δi dc (ϕ m ) for different values of M and cos(ϕ v ) = 1.The analytic derivations were again verified in a simulation with ideal semiconductor switches in MATLAB/Simulink.The basic simulation parameters were selected to be the same as in Section III-B.Fig. 7 shows the simulated waveform of the DC-link current i dc over one period of the output currents along with the analytically derived enveloping curve calculated using (9).The analytic computation Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply. of the current ripple shows good agreement with the simulated values.Occurring deviations are due to the ripple of the output voltage, which is neglected in the analytic derivation.
The maximum value of the current ripple Δi dc max for cos(ϕ v ) = 1, can be calculated by analyzing (9) which, by transforming, yields an estimation formula for L dc .It occurs at Although Δi dc can become larger than the value given in (10) for cos(ϕ v ) < 1, this only happens from about cos(ϕ v ) ≈ 0.83.The results of the derived calculation method correspond to the methods often found in the literature [18], [20].
Regarding the saturation of the DC-link inductance, based on the (10) transformed to Δi dc max , the maximum current through the DC-link inductance i dc max can be calculated by (11) by addition to the mean value of the DC-link current i dc .
The RMS value of the DC-link current I dc necessary for estimating the copper losses in the inductance can only be calculated approximately.It is composed of the constant average DC-link current i dc and the AC component i dc .As a simplification, it is assumed that i dc has a pure triangular shape.It can therefore be obtained from the peak value of (9) and the crest factor √ 3 for triangular signals in (12).
The equation was evaluated numerically for unity power factor cos ϕ v = 1.Here, the maximum AC component occurs at about M ≈ 0.7 and can be calculated by Thus, the maximum RMS value of the DC-link current I dc max can be estimated by (14).
To determine the volume and the occupied board area of the passive components of the current-source inverter topology, the derived design parameters presented in the previous two sections were used.The volume for filter capacitors is estimated by selecting suitable components available on the market and optimizing their volume and board area respectively.The DClink inductance design is based on a method presented in the literature [21], which aims to optimize the volume and losses of DC-link inductances for CSIs.The optimization results for both the filter capacitors and the DC-link inductor are then analytically interpolated to obtain empirical estimation formulas for further optimization steps.

IV. DESIGN OF THE FILTER CAPACITORS
For the determination of board area and volume of the filter capacitors a database was created from the available components of the manufacturers Murata [22], TDK [23] and KEMET [24].Surface mountable multi-layer ceramic capacitors (MLCCs) utilizing the Class I dielectric C0G (NP0) according to standard EIA-198-1-F-2002 were considered for selection.Capacitors based on this dielectric offer excellent temperature stability, low ESR and good DC bias performance at the cost of lower capacitance per volume at a certain rated voltage.The extremely low ESR of MLCCs based on these dielectric materials results in negligible losses in these devices.Therefore, many manufacturers do not specify concrete values for the maximum permissible ripple current.In most cases, only the ESR over the frequency is specified.For instance, the one of the eight parallel volume optimised MLCCs from the following design example in Section IV-A has an ESR of 2.74 mΩ at a frequency of 100 kHz, resulting in dielectric losses of approximately 2 mW per capacitor at the computed maximum RMS current flowing through them.Ceramic capacitors with higher class, ferroelectric dielectrics such as X7R or X5R should not be used for applications in CSIs, as these are usually only specified for DC voltages and feature considerably higher losses.Nevertheless, even when designing with MLCCs with Class I dielectrics, the expected losses should be checked after component selection.
The volume per capacitance and the PCB area required per capacitance were then optimised using the database built up by the aforementioned manufacturers.Parallel connection of several capacitors to increase the capacitance and series connection to increase the maximum voltage were also taken into account.The area and volume calculations for both single and multiple components considered the minimum tolerable distances between components according to IPC-7351 Density Level C: Minimum (Least) Land Protrusion.
For the estimation of optimal volume and board area per capacitance of a configuration consisting of a number of individual capacitors, a maximum tolerable rated voltage V r ref is defined in the first step.Only capacitor configurations with an actual rated voltage V r > V r ref are considered for further optimization.From Fig. 8. Graphical visualization of the optimization process for the volume of the filter capacitors.Each dot represents a capacitor arrangement that can be single parts or a combination of series and parallel connection of several components with a total rated voltage V r > 100 V.Besides the linearized configuration with highest capacitance per volume for V r > 100 V the fronts for several different higher voltages are depicted as well.
these configurations, those with the smallest volume or board area per capacitance are determined.Since these relationships are approximately linear, the determined component values can be interpolated with a straight line.Thus, for a selected voltage V r ref , an optimum relative capacitance per volume C V (relative capacitance in Fm −3 ) or board area C A (relative capacitance in Fm −2 ) can be specified representing these straight lines.Fig. 8 shows a graphical visualization of this process for the volume of filter capacitors.A point corresponds to a capacitor configuration consisting of one or more individual components connected in parallel or in series, all of which have a rated voltage V r > 100 V.The capacitance of each configuration is plotted over the volume and the color coding symbolizes V r .The straight lines approximate the points with largest capacitance per volume of a certain V r .
This procedure was then performed several times for V r ref between 50 V and 1.8 kV in 25 V steps.The results of all calculations for relative capacitance per volume C V is shown in Fig. 9.A point there represents the slope of one of the determined straight lines.From this diagram, a general relationship between capacitance per volume and rated voltage can then be read for available MLCCs with Class I dielectric.Fig. 9 shows this curve for volume per capacitance obtained from the optimization.The discrete levels arise from the fact that the rated voltage of the individual components is sometimes only available in rough steps (e.g. 100 V, 250 V, 350 V, ...).
Both this relationship and the relationship for the occupied board area are then fitted with the two-term exponential model shown in (15).
The relative capacitance per board area C A can also be determined using (15).The parameters of both fit models can be read from table Table I.

TABLE I PARAMETERS OF THE TWO-TERM EXPONENTIAL MODELS FOR THE ANALYTIC VOLUME AND AREA FIT
Using these two models and the associated parameters, a power electronics design engineer can make a simple estimate of the approximate volume or board area required for the filter capacitors of a CSI without having to perform a complicated optimization.

A. Filter Capacitor Design Example
To make things clearer, a short design example is carried out.The filter capacitors of a CSI with an output power of P ac = 5 kW at a line-to-line RMS output voltage of V ac ll = 400 V (V ac = 231 V) are to be designed.The peak value of the output current and thus the necessary DC-link current in this case corresponds to The PWM switching frequency is f pwm = 100 kHz and the maximum tolerable voltage ripple is set as Δv max = 5% V ac √ 2 = 32.7 V.By using (4), ( 5) and ( 7), the filter capacitance C f = 1.56 μF, the peak value of the voltage v C max = 343 V at and the RMS current through the filter capacitance I C max = 5.59A can be calculated.
Using (15) and the parameters from Table I and a safety factor for the maximum capacitor voltage of 30%, the optimal volume can now be estimated with 3 or the optimal consumed board area can be estimated with For this case, the volume optimal capacitor configuration with 8 parallel connected components of type C2220C204KCGLCAUTO has a volume of 1.51 cm 3 and the board area optimal capacitor configuration with 2 parallel connected components of type CKC33C884KCGLC7805 has an Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.area of 2.16 cm 2 .The small deviations between these and the estimated values are due to the large steps between the available rated voltage values.

V. DESIGN OF THE DC-LINK INDUCTOR
The calculation for volume and the required board area of the DC-link inductor is based loosely, as already shown in [1], on the method demonstrated in [21].However, in the present publication, major improvements have been made to this.Here, the optimization is performed directly with commercially available torroidal core geometries and their data.The most important geometrical parameters for the inductance determination, the mean magnetic path length and the cross-sectional area of the torroid, are taken directly from the manufacturer.Furthermore, the relative permeability μ r (H) provided by the manufacturer is used directly instead of the analytically fitted equation for B(H) to account for the saturation behavior of the cores.In addition, in the present optimization the determination of the copper losses and the actual volume of the inductors is greatly improved and the optimization is performed for a wider range of materials with different relative permeabilities.Finally, as for the filter capacitors, a general prediction method is presented to determine the optimum volume or board area with respect to the required inductance and DC-link current.
In the design method presented, an attempt is made to minimize the volume or board area and total losses consisting of core losses and copper losses.For the cores used, toroidal powder cores with molypermalloy (MPP) material from the manufacturer Magnetics are investigated.This manufacturer provides analytic fit equations for the B(H) curve and differential relative permeability μ r (H) curve, as well as the Steinmetz parameters K c , α and β for the offered materials and cores [25].The geometrical parameters of toroidal cores are given in the form of outer diameter D c , inner diameter d c , height h c , core volume V c , core cross-sectional area A c and mean magnetic path length l c .The design process is performed numerically for each available core geometry (the outer diameters range from 4.19 mm to 167.21 mm) with each available material featuring a nominal relative permeability between 14 and 550.The initial parameters for the optimization are the desired values for the inductance L, the PWM frequency f pwm , the average DC-link current i dc and the RMS value of the AC component of the DC-link current i dc max known from the design process.

A. Determination of the Number of Turns
At the beginning of the optimization, a core geometry with a nominal relative permeability is selected from the manufacturer's data.Then, the number of turns N around the core is increased stepwise and the mean magnetic field strength H is calculated by ( 16) at each increment.
Here, i dc is the expected average DC-link current through the inductor.In each step, the inductance L for the given number of windings can then be calculated using (17).
Here, μ r (H) is determined via the analytic relationship specified by the manufacturer.The process of stepwise increase of N is performed until L is larger than the desired inductance.If the number of turns calculated would lead to too much saturation (e.g. if μ r (H) deviates too much from the nominal value), the core format used is already discarded after this step because the desired inductance can not be realised.

B. Determination of the Core Losses
After determining the number of turns, the core losses can be estimated using the Steinmetz parameters provided by the manufacturer.For this purpose, it is assumed that on average the largest core losses occur when the AC component of the DC-link current has the largest RMS value.This occurs, as already mentioned in Section III-C for M ≈ 0.7, and can be calculated using (13).For a simple estimation, the calculated RMS value i dc max is then doubled and multiplied by the factor √ 3 for triangular signals to obtain the peak-to-peak value of an equivalent triangular signal.from this, similar to ( 16), a field strength ripple ΔH is calculated, which is superimposed on the constant mean field strength.Assuming that ΔH << H, the flux density of the B-H curve changes little in the area of the ripple and can therefore be assumed to be linear in that range with slope μ r (H).The ripple of the magnetic flux density ΔB can then be calculated by (18).
If ΔB is now substituted into the Steinmetz equation in (19), the maximum core losses occurring during the operation of the converter can be estimated.
The two factors of 1000 each come from the fact that in the Steinmetz equation the frequency is put in kHz, and the relative power dissipation per volume is put in mWcm −3 .

C. Determination of the Copper Losses
For the calculation of the copper losses as well as the total volume of the wound inductor, a method is used which is based on the actual winding process and does not use filling factors as in [21].Therefore, a wire diameter is selected from a set of diameters (AWG 1 to 50).This wire is then iteratively wound onto the core by an algorithm starting with the first layer.If the desired number of turns can not be achieved by winding one layer another one is applied.The inner diameter of the inductor (window area) for the application of a new layer decreases with the number of layers.The possible number of turns of the kth layer, N k max can be calculated with (20).
Here, R w = D w 2 is the wire radius and r = d 2 represents the core inner radius.In this model, it is assumed that one layer reduces the usable inner radius of the core window area by D w and that the outer diameter and the height of the total wound coil increase by 2 D w per layer.If the inner usable diameter of the core respectively the window area is reduced to zero by selecting a wire that is too thick, the desired number of turns cannot be realized with this diameter, and the process is aborted and started with the next wire from the set.
The length of the wire increases per wound layer k by the number of windings applied (N k = N k max for a full layer, potentially less in the last layer K) and can be calculated by The total wire length l w is the sum of the calculated lengths of the individual layers (l w = K k=1 l k ).The volume V L occupied board area A L (horizontal position) and inductor surface area A s (for estimation of the inductor heating) of the inductor can then be calculated using the core outer dimensions increased by the winding according to (22).
After determining the wire length and the number of layers, the DC resistance R of the winding can be calculated through where the specific resistivity of copper ρ cu is assumed to be 0.0178 Ωmm 2 m −1 .For the calculation of AC resistance R, which occurs due to skin and proximity effect, the method from [26], [27] is applied as described in [21].Equation (24) shows the relationship for the computation of the AC resistance R n for each harmonic order n of the AC current. where with the parameters: r δ: skin depth r η: porosity factor r D w : wire diameter r n: harmonic order r f pwm : PWM frequency (fundamental frequency triangular waveform) r ρ cu : relative conductivity copper r t: distance between two adjacent conductors (here, t = D w was assumed) The functions "ber" and "bei" represent the Kelvin functions based on the Bessel function of the first kind and order ν, J ν (z), where ber For the zero-order Bessel-and Kelvin functions ν = 0 the subscript is not written.The required derivative of the zero-order Kelvin functions can be solved analytically by The AC component of the DC-link current is again assumed to be a simple triangular signal with an RMS value of i dc max according to (13).From this, an equivalent amplitude can again be calculated with the factor √ 3. The Fourier coefficients I n , which are necessary for the calculation of the AC copper losses P cu , can therefore calculated by The estimated AC losses P cu , including skin and proximity effect, can then be obtained from the sum of the individual power losses.An equivalent AC resistance R can be determined by the assumed current RMS value.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
For practical reasons, the harmonic coefficients are calculated only up to the 9th order, since from this point the harmonic current amplitude is less than 1% of the fundamental amplitude.
Once the copper and core losses are determined, the temperature rise T rise can be calculated as shown in [21] using (30) from [28].The factor 1  10 comes from the fact that for this equation in this publication, every power variable is assumed to be in W and the surface area is assumed to be in m 2 .
Since the increase of the inductor temperature T from its initial Temperature T 0 affects the specific resistivity of the copper ρ cu , the copper resistances (AC and DC) are adjusted to the elevated temperature according to (31).
The specific temperature coefficient of copper here is α = 0.00404 / • C. Based on the new DC resistance at the elevated temperature, the corresponding new AC and DC copper losses can now be recalculated by ( 24) and ( 29) and a resulting temperature rise according to (30) can be determined.This process is continued iteratively until the inductor temperature has reached a steady state.In practice, the number of iterations is limited to four, since the final temperature changes by less than 1% for further iterations [21].
With the consideration of the temperature rise the design of an inductor is completed.From the evaluated parameters, a figure of merit can be obtained for each analyzed core with all determined winding geometries, which is necessary for the calculation of the optimal design.For the optimization of the volume FOM V and for the optimization of the board area FOM A is given in (32).
For the selection of the optimized inductance, the inductance with the lowest figure of merit is chosen from the set of generated ones.Fig. 10 shows a graphical visualization of the described design process of the DC-link inductor for optimising its volume.Each point represents an inductor design with its own core geometry and winding configuration for a given set of input parameters.The Red Cross marks the optimal design selected based on the respective figure of merit in (32).

D. Experimental Verification of the Design Process
To verify the demonstrated design process for the inductors, one inductor was practically realised.Measurements were then carried out with this built inductor and its determined parameters were compared with the theoretical values from the design process.
The input parameters for the design of the component included an inductance value of 100 μH at an average current of 5 A, with a current ripple of 1.25 A at a switching frequency of 100 kHz.Based on these specifications, the design process   II.
To verify the calculated inductor, it was wound and its parameters were measured and compared with the theoretical values.The inductor was first tested at a selected DC-bias of 5 A. To accomplish this, a square-wave voltage with a duty cycle of 50% and variable amplitude was generated using a half-bridge circuit.The voltage was then fed to the inductor under test via a resistor with a large filter capacitor (2200 μF).The resistors value and the amplitude of the voltage were adjusted until the desired triangular current with an amplitude of 1.25 A and a DC-bias of 5 A was obtained.The capacitor maintained a constant voltage at the resistor, preventing the linear parts of the current waveform from being influenced by the resistor.The basic circuit diagram for this experiment is shown in Fig. 11.The voltage v L and current i measurements for the circuit's inductor were taken at the operating point selected in the design process, as shown in Fig. 12.Both waveforms were captured using an oscilloscope (LeCroy WaveRunner HRO 66Zi).
The expected triangular shape was observed for the current waveform, while the voltage waveform across the inductor appeared rectangular and exhibited almost no DC-bias.Although there was an overshoot at the transitions of the voltage due to the switching behavior of the half-bridge, this did not affect the measurement.The inductance was determined during time intervals where the voltage remained constant and the current increased linearly, using the equation L = v L ,Δt Δi .Here, v L denotes the mean value of the voltage, Δt is the duration, and Δi is the linear change in current over the time period.The measured inductance for the conducted experiment was found to be L = 105 μH.This result is in close agreement with the expected inductance of 100 μH.
Measuring the losses occurring in an inductor, such as DC and AC copper losses and core losses, can be challenging due to the reactive power present in the component, which considerably exceeds the active power.In the circuit presented here, reactive power of approximately 125 W is added or removed during half a period, whereas the calculated active losses are only 671 mW.
To avoid this problem, we measured only the temperature rise of the inductor in still air and compared it with the value determined during the design process.
We used a thermal camera to capture a thermal image of the inductor after 30 min of operation at an ambient temperature of 21.5 • C, as shown in Fig. 13.The final temperature of the inductor was 34.6 • C, corresponding to a temperature increase of 13.1 • C. The design process had predicted a temperature rise of 10.4 • C, which slightly underestimated the actual measured value.Based on these results, we conclude that the design process for the inductors is sufficiently accurate and can be used to optimize the inductor in terms of volume and occupied board area.

E. Interpolation of the Inductor Designs
The proposed optimization was now performed for different sets of input parameters (L dc , i dc , i dc max , and f pwm ) and the optimal volume or board area was acquired for each inductor.By further analysis of the obtained data, it can be seen that the inductance per volume or board area roughly follows a linear relationship which can be expressed by an inductance per volume L V (relative inductance in Hm −3 ) or inductance per board area (relative inductance in Hm −2 ).The graphical visualization of such an analysis process is shown in Fig. 14 where one dot represents an optimised inductor for a given set of input parameters.The variation of the individual designs is mainly due to the variance of the available core formats.For larger inductance values, fewer formats are available, which results in a greater dispersion of the optimization results.
By linearising the optimized values as inductance per volume or area, similar to the filter capacitors, these values can now be plotted against the average DC-link current i dc at a given PWM frequency.
Fig. 15 shows the obtained correlations for the inductance per volume at f pwm = 50 kHz, 100 kHz and 200 kHz and different DC-link currents in the range of i dc = 0.5 A . . .20 A. These correlations were then fitted with the model from (33), which interpolates the simulated values very well, to obtain an analytical relationship for estimating the volume and required board area.The calculated values for the selected frequency, DC-link current, and inductance range show that the optimized inductance per volume or unit area decreases sharply, especially for medium DC-link currents i dc < 6 A, independent of f pwm , and then remains approximately constant for the higher current range.The difference between various selected PWM frequencies is visible (higher switching frequencies lead to an increased volume or area due to the increased core and AC copper losses) but does not have nearly as large an effect as the DC-link current.Using these models and the associated parameters, a simple estimate of the approximate volume or area required for the DC-link inductance can be made, as for the filter capacitors, without having to perform a complicated optimisation.

F. DC-Link Inductor Example
As for the filter capacitors, a short design example is carried out.The DC-link inductor of a CSI with the same parameters as in the previous example (P ac = 5 kW, V ac ll = 400 V, I dc = 10.2A, f pwm = 100 kHz) is to be designed.The the maximum tolerable DC-link current ripple is Δi dc max = 25% I dc = 2.55 A.
By using (17), a DC-link inductance of L dc 379 can be Using (33) and the parameters from Table III, the optimal volume can now be estimated by V est = L dc L V (i dc =10.2 A) = 57.3cm 3 or the optimal consumed board area can be estimated by A est = L dc L A (i dc =10.2 A) = 29.2cm 2 without having to perform a complicated optimization.For this case, the actual volume optimal inductor and the area optimal inductor based on the presented optimisation method have the same core and winding configuration.This is constructed from the core C055439A2 with a nominal relative permeability of μ r = 60 having N = 62 turns with a wire diameter D w = 1.6 mm.The volume of this inductor is 58.6 cm 3 and the occupied board area in horizontal position is 23.0 cm 2 .Both values show good agreement with the estimated results.

VI. SUMMARY OF VOLUME AND BOARD AREA ESTIMATION
From the results obtained in Section IV, it can be seen that the volume and board area of the ceramic capacitors based on the C0G/NP0 dielectric depend in principle only on the rated voltage V r of the individual components and thus almost only on the maximum RMS output voltage V ac .For power factors of load cos(ϕ) = 1, the voltage ripple to (5) must also be taken into account.Since the optimum volume and board area for a certain rated voltage of the entire structure behave approximately linear to the capacitance, the relationship can be expressed by a capacitance per volume C V or capacitance per area C A which can be determined for the investigated component types according to the empirically determined relationship from (15).
For determining the optimum DC-link inductance, the optimization process in Section V is slightly more complex.However, as for the capacitances, there is an approximately linear relationship between inductance and volume or required board area in the realizable inductance range with the investigated core geometries.This can again be expressed by an inductance per volume L V or area L A , which depend on the DC-link current, the ac component of the DC-link current and the PWM frequency.In the investigations, the maximum AC component of the current was set to 5% of the intermediate circuit current to lock one optimization variable.If this relative inductance is now examined over the average value of the DC-link current, a relationship is found which can be estimated analytically with the power model from (33).The optimal relative inductance changes significantly for small average DC-link currents (i dc < 6 A) and remains approximately constant for larger currents (i dc > 10 A).The PWM frequency has little effect on the inductance and is represented by different model parameters.

Fig. 4 .
Fig. 4. Normalized peak-to-peak value of the output voltage ripple of phase a at different modulating indices M .A maximum of Δv a C f fpwm I dc = 0.25 appears

Fig. 5 .
Fig. 5.One period of the simulated sinusoidal inverter output voltage of phase a.The envelope curve represents analytically computed values from (3).

Fig. 7 .
Fig. 7. DC-link current over one period of the simulated sinusoidal inverter output.The envelope curve represents analytically computed values from (9).

Fig. 9 .
Fig. 9. Volume optimized capacitance per volume of the selected filter capacitors plotted against the rated voltage.The values obtained were interpolated with a two-term exponential model to obtain an analytical relationship.

Fig. 10 .
Fig. 10.Graphical visualization of a DC-link inductor design process with input parameters L = 100 μH, i dc = 10 A, i dc max = 1.5 A, f pwm = 100 kHz and T rise < 150 • C. Each point corresponds to a possible design and is plotted according to the estimated total losses (P c + P cu + P cu ) and the calculated volume V L .The optimal design determined based on the selected figure of merit is marked with a red cross.

Fig. 13 .
Fig.13.Thermal image of the built inductor when supplied with a triangular current with an average value of 5 A and a current ripple of 1.25 A. The picture was taken after 30 minutes when the temperature in still air has reached its steady state.

Fig. 14 . 3 =Fig. 15 . 3 .
Fig. 14.Optimized set of inductances (L dc = 20 μH . . .500 μH in 20 μH steps) for an average DC-link current of i dc = 10 A and a RMS value of the AC component of i dc = 25% i dc √ 3 = 722 mA.The values were interpolated with a straight line approximating a constant relationship L dc V Lfor the selected operating point.

TABLE II INPUT
ANDOUTPUT PARAMETERS OF THE DESIGN PROCESS CARRIED OUT FOR A SPECIFIC INDUCTOR selected the C055894A2 core with 38 turns and a wire diameter of 1.5 mm for the component.A summary of the inductance parameters is presented in Table

Table III
shows the parameters for the fit equation of the volume and area optimization.For different switching frequencies in the Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE III PARAMETERS
OF THE POWER MODELS FOR THE ANALYTIC VOLUME AND AREA FIT