Comparison of SVPWM Techniques Under Switching Loss Control for Induction Motor Drive With LC Filters

Only precise industrial applications can benefit from the high-frequency performance of variable-speed drives with low switching losses. A five-phase induction motor (FPIM) is connected to a voltage source inverter (VSI) via a <inline-formula><tex-math notation="LaTeX">$LC$</tex-math></inline-formula> filter (low pass filter) to reduce high-frequency losses in the motor. A five-phase sinusoidal voltage is used to lower the high <inline-formula><tex-math notation="LaTeX">$dv/dt$</tex-math></inline-formula> at the motor terminals. However, sustained resonant frequency oscillations destabilize closed-loop control of the FPIM drive at certain operational points. This paper presents and analyzes a variety of high-frequency SVPWM techniques, both continuous and discontinuous. It is also possible to optimize the switching frequency of the five-phase two-level VSI fed FPIM drive using an improved current ripple prediction method. Auxiliary circuits and high-frequency sensors are not necessary in this system, making it more stable. Simulated and experimental results are used to evaluate the stability of a drive under a variety of conditions.

across L x f and phase voltage of the FPIM, respectively. S x , S x switching functions applied to upper and lower switches, respectively. C dcu , C dcl upper and lower DC-link capacitor, respectively. f s , f sw , f sa denote the rated supply frequency, the switching frequency of the VSI, and the sampling frequency of the controller, respectively. I s , V sl denote the rated stator current and the rated motor voltage, respectively. R s , R r represent the stator resistance and the rotor resistance, respectively. L ls , L lr , L m represent stator leakage inductance, rotor leakage inductance, and magnetizing inductance, respectively.

I. INTRODUCTION
M ULTIPHASE variable speed drives (VSD) received considerable attention due to the increased efficiency for high-power industrial applications. Compared to other multiphase drives, five-phase drives have significant advantages, such as torque ripple reduction and fault tolerance capability [1], [2], [3]. Due to their advantageous properties, five-phase drives prevail among multiphase drives [4], [5], [6]. In this paper,a five-phase induction motor (FPIM) drive is used as a case study. Different five-phase multi-level inverters feeding FPIM are less demanding in industrial applications due to performance constraints caused by control complexity and vulnerability to This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ switching failures [4]. Therefore, as a result of the above analysis, the voltage source inverter (VSI) with a five-phase two-level (FPTL) platform is selected as the FPIM supply option [7].
For VSI-fed multiphase drives without filter, several closedloop control approaches have been developed. These include sensorless rotor flux (field) oriented control (FOC) [8]; direct torque control (DTC) [7], [9] for improved steady-state and dynamic response; model predictive control (MPC) [10], [11] to obtain optimal performance within user-defined constraints during model parameter variations; and fuzzy logic-based finitetime and command-filtered adaptive backstepping control [12] to handle uncertainties such as input saturation, external load disturbances. DTC and MPC provide variable switching frequency to obtain optimal flux and torque requirements, while FOC and direct self-control strategies [7] utilize several carrierbased pulse width modulation (PWM) techniques [13]. PWM control techniques are commonly adopted in three-phase [14] and multiphase VSI [15] to control its output voltage and improve harmonic distortion. For various FPIM closed-loop controls, the space-vector PWM (SVPWM) scheme is intended to minimize switching losses by providing a one-state transition at any time and maintaining a constant switching frequency. DC bus utilization is higher in SVPWM, so it is widely used for VSI with a five-phase configuration [6]. Based on the placement of null vectors, SVPWM is divided into seven different categories and further divided into conventional SVPWM, two types of continuous PWM (CPWM), and four types of discontinuous PWM (DPWM) mode [4], [16], [17]. In these DPWM schemes, one VSI leg is clamped to a fixed switching state through each switching cycle, whereas high-frequency switching takes place on another four legs; thus, it reduces the overall switching loss of VSI. Hence, the impact of FOC with these SVPWM schemes is investigated in this paper for the FPIM drive.
In such VSDs, the applied stator voltages are not purely sinusoidal, as in the case where the stator is supplied through direct AC lines. Furthermore, the stator current and the developed motor torque contain higher ripples, and the stator windings are subjected to higher voltage stress due to repetitive pulses [18]. To overcome this, LC passive filters with different configurations can be used between the FPTL VSI and the FPIM stator terminals [19], [20]. In [21], a high-power medium voltage VSD with LC passive filter is investigated, which utilizes a three-phase induction motor (TPIM) driven by a three-level VSI operated at a lower switching frequency. In these types of drives, the residual life of the motor is enhanced with reduced electromagnetic interference. Furthermore, the incidence of motor bearing failures is also reduced as a result of the elimination of common-mode voltage and the minimization of motor bearing currents [6], [7]. As a side effect of these LC filters, the performance of the field-oriented control (FOC) of the motors is greatly hampered due to constant resonance frequency oscillations, which directly affect the steady state as well as the transient behavior of the VSD [22]. In such a scenario, a predictive controller with a fast transient response is investigated in [23] without overpowering the resonant frequency oscillations. To overcome such challenges in grid-tied converters, single-loop or multiloop controllers based on the control signal shaping technique are investigated [24]. Moreover, various active damping (AD) methods have also been proposed in literature to attenuate such unwanted oscillations in VSD [25]. Thus, the active power losses that occur in the damping resistors can be eliminated in the VSD, where a passive LC filter is used. Hence, this paper investigates such an active damping technique for the FPIM based VSD. For an FPIM-based VSD integrating filter based on an adaptive full-order observer [9], [24], a modified vector control technique with cascaded loop is a better solution. For such a type of observer, fewer sensors are needed to sense the dc-link voltage and the output current of the VSI. Observers, on the other hand, estimate the actual motor parameters, such as voltage, current, and speed. However, being a competent observer is a tough and time-consuming task. In addition, additional sensors and PI controllers are necessary to regulate state variables such as inductor currents and capacitor voltage in the LC filter [26]. Compared to [26], this paper has the following significant contributions. 1) A zero sequence injection-based SVPWM, CPWM and DPWM techniques are proposed in Section II that employs low computational burden to digital signal processor (DSP). 2) The current ripple prediction (CRP) technique replaces zero-crossing detection circuits, and therefore no additional auxiliary circuits or current sensors are required to determine the switching frequency (f sw ) for developed PWM strategies. 3) An appropriate control methodology is proposed in Section III for an FPTL-VSI fed FPIM drive with LC filter. An integrated observer is also designed that performs sensorless speed operation of the proposed drive. 4) Section IV presents an experimental validation result of the FPIM drive at a wide range of speed variation. A comparison study also established between proposed SVPWM, CPWM and DPWM schemes.

II. FILTER DESIGN AND PWM STRATEGIES
As illustrated in Fig. 1, a five-phase second-order low-pass sinusoidal LC filter has been designed for an IGBT-based FPTL VSI-fed 5 hp, 220 V, 3.99 A, 4 pole, 50 Hz, star-connected, FPIM drive. FPTL VSI switching functions, S x and S x , are complementary to each other and can represent states 0 or 1. The FPTL-VSI has 32 (2 5 ) possible switching states/voltage vectors. These 32 switching states/voltage vectors are divided into four  Fig. 2(a). The corresponding VVs in xy-plane are represented in Fig. 2(b). Several PWM schemes are discussed in this section that incorporate these voltage vectors, either directly or indirectly.

A. Filter Designing and Its Impact
To achieve stable drive performance with the LC filter, a proper design of the AC and DC side filters is essential.

1) Calculation of Filter
Inductance L x f : The magnitude of L x f is calculated considering two design criteria [27], [28]. The first criterion is that the value of the switching ripple current (Δi x i ) through L x f is within 15-25% of the peak value of i x i , which is assumed as the rated stator current of the FPIM drive [29]. The second criterion is that v x f at the rated I s and f s should not exceed 3% of V sl [27], [28]. However, the selection of L x f is basically a design trade-off between the maximum current ripple and the size of L x f ; however, C x f is considered according to the availability of a close approximation to the designed value [30]. The expressions of Δi x i and v x f are written as (1).
Here, the value of Δi x i is considered 20% of the peak value of the rated i x i . With this consideration, L x f is calculated as 1.15 mH for v dc = 600 V at f sw = 50 kHz. However, the designed value of the prototype inductor is 1.21 ± 5% mH with an internal resistance of r x f = 0.3 ± 5% Ω, which is a close approximation to the calculated value. From (1), v x f across L x f can be calculated as 0.878% of V sl in V sl = 220 V and f s = 50 Hz.
2) Calculation of Filter Capacitance C x f : The filter capacitance is computed based on the reactive power demand of the squirrel cage FPIM, which must be provided by C x f , and only the active power demand must be supplied by the VSI [30]. The reactive power is solely accountable for energizing the magnetic core of the FPIM to generate the requisite air-gap flux, and its demand is nearly constant regardless of whether the FPIM is operating at full or no load. Only the active power demand is varied with load change. Because the reactive power demand of the FPIM operated without load at 50 Hz is greater than the active power demand, the no-load power factor of the FPIM is lower than its full load power factor. Therefore, the active power demand of the FPIM and the reactive power demand of L x f are supplied from the VSI. The reactive power demand (Q nl ) of the FPIM is supplied from the filter capacitor [30], which can be expressed as (2).
To accommodate all the reactive power requirements of FPIM, the value of C x f needs to be large enough. The larger sized filter capacitor may not be useful for various size-constrained applications. Therefore, the capacitor is designed in this study on the basis of the reduction in voltage ripple at the stator end of FPIM. Now, the filter capacitor C x f can be obtained as (3) using (2).
From the no-load test of FPIM, the per-phase data are collected for stator voltage (V nl = 221.28 V ), stator current (I nl = 0.744 A) and active power demand (P nl = 50.53 W). Now, the perphase reactive power (Q nl = V 2 nl I 2 nl − P 2 nl ) can be computed to get a value of 156.69 VAr. Using (2) and (3), C x f can be calculated as 10.186 μF. However, the capacitance value chooses higher than the calculated value due to the availability constraint.
3) DC-Link Capacitance Design: The DC-link capacitance selection depends on the power rating of FPTL-VSI. The complete details of selecting the DC-link capacitors are presented in [6]. The values of C dcu and C dcl are considered equal for computation simplicity; however, due to manufacturing tolerances, the actual values may differ. Again, at different speeds, the DC link voltage utilization differs and the DC-link current requirement will be higher considering the full load torque. Hence, for this particular study, the DC-link capacitors are designed as (4).
Low speed (4) where ω mh and ω ml represent the high and low speeds of FPIM, respectively. δ r represents the variable that depends upon the modulation index of the FPTL-VSI and the DC-link voltage ripple. Considering the FPIM rated current of 4 A/phase, the maximum transient current of the DC-link can be calculated as At ω mh = 1500 rpm and v dc = 600 V, the the DC-link capacitance (C dc ) can be computed as ≈ 200 μF, while at ω ml = 100 rpm, C dc is evaluated as ≈ 2100 μF with 5% variation in v dc . The DC-link voltage is shared by two 4700 μF/450 V capacitors selected from the available capacitor range in accordance with the above calculations.

B. Proposed Generalized PWM Scheme for FPTL-VSI
The proposed generalized PWM scheme has been developed by comparing the reference modulating signal (d x * s ) with a triangular carrier signal. d x * s can be obtained by adding the modulating signal (d x s ) to the zero sequence component (d z ), as per (5) [31].
By dividing v dc 2 on both sides of (6), the relation for d z can be obtained as (7).
where d max and d min are considered as the maximum and minimum value of d x s , respectively, at a given instant. Through further manipulation, i.e., adding and subtracting 1/2 in the right-hand side of (7), d z can be written as (8).
To illustrate various SVPWMs in Figs. 3 and 4 with appropriate selection of zero vector V 0 or V 31 , the distribution factor k can be introduced for (8) to obtain (9). In order to achieve it, the maximum duty d max can be selected for k period and in contrary, d min can be selected for (1 − k) duration, considering the maximum duty of 1.
A further simplification of (9) yields the relation of d z in (10).
The selection of the distribution factor k ∈ [0, 1] depends on the SVPWM technique, which can be observed analytically from the relation given in (11).

SVPWM and CPWM Scheme
where  Fig. 4 for both CPWM (CPWM1 and CPWM2) and DPWM (DPWM0, DPWM1, DPWM2, DPWM3) schemes. It is observed that, for any sector, the DPWM modulating signal consists of CPWM1 and CPWM2 modulating signals. For illustration, DPWM follows CPWM1 and CPWM2 for the period 54°to 90°and 90°to 126°, respectively. Hence, the analysis of current ripple in the case of DPWM can be carried out directly from both CPWMs. For sector 1, waveforms of gate signals and current through inductors are graphically presented in Fig. 5 for CPWM1 and CPWM2, respectively. The appropriate implementation of null vectors '11111' and '00000' are considered for both CPWM schemes. In Fig. 5, the modulating signal d * sd is kept OFF for CPWM1, so the corresponding switch S d stays on throughout the switching period. The modulating signal d * sa is kept ON for CPWM2, so S a is kept OFF over the entire switching period. Therefore, high-speed switching events occur on the remaining eight switches.

C. CRP Analysis and f sw Selection With P sw Control
The Fig. 5 is utilized to analyze the current ripple in the inverter side (i x i ) considering FPIM side current (i x s ) as the reference. Ripple content in i x i is high due to the lower value of L f . It is assumed in this analysis that the stator current i x s is free from ripple components. Therefore, i x s current is equated to the average value of i x i over a switching period. As the carrier wave is symmetrical, the interrelationship within i x i and i x s is expressed by (12).
where i th is the minimum current that is utilized to charge or discharge the VSI internal switch capacitance. The effect of CPWM1 and CPWM2 on FPTL VSI is considered for detailed analysis. As per (13), essential conditions can be written again according to the ripple current of the inductor which is placed on the inverter side.
where Δt x = d x * s /f sw is the 'ON' time period of x th -leg upper switch. The variable m varies over time and does not depend on the sequence x. The switching frequency (f sw ) of the carrier waveform can be obtained as (14) using (12)-(13). As L x f is coupled with Δi x i , increase in L x f leads to a decrease in Δi x i , resulting in minimal changes in the denominator product L x f Δi x i of (14). Hence, the parameter variations do not affect much for the estimation of f sw . The block diagram representation of f sw selection for carrier signal generation is illustrated in Fig. 6. In the proposed SVPWM strategy, there is only one switching state change that incorporates switching activities of two switches. Hence, the switching power loss (P sw ) can be further calculated according to (15).
where V GE± is the driving voltage of the VSI switches and Q G is the gate charge of the switching device. By controlling f sw , P sw can be controlled.

III. FPIM DRIVE CONTROL AND OBSERVER DESIGN
The proposed controller accumulates the advantages of FOC with switching loss control. In this section, the FOC methodology is first elaborated, followed by the filter control strategy. An observer is implemented to estimate the speed and internal state of the FPIM drive system. The details of the complete control strategy are illustrated in Fig. 7.

A. FPIM Drive Control Using Proposed SVPWM Strategy
To achieve better drive stability, FOC is proven to be a better control approach. FOC is considered mostly motor parameter dependent; however, the motor parameters are not utilized in Here, S abcde and S a b c d e are the switching pulses and their complements to control the IGBT switches, as illustrated in Fig. 1. Internally, S abcde is used as feedback through a unit delay. After generating phase voltages and phase currents, v dq i and i dq i can be generated through (16) by considering the generic variable X ∈ {v i , i i } [7].
Step-3: The estimated value of the rotor angular speed (ω m ) along with the rotor position (θ r ) can be generated from the observer designed in Section III-B. In addition, the observer provides the estimated value of stator voltage (v dq s ), stator current (î dq s ) and stator flux (ψ dq s ) in dq-domain by utilizing the transformations mentioned in (16). The inputs to the observer are v dq i and i dq i , as shown in Fig. 7.
Step-4. FOC strategy: The estimated value ofω m is compared to the reference value of the angular speed of the rotor (ω * m ) and the corresponding speed tracking error (ω err = ω * m −ω m ) is controlled by a simple PI controller (speed regulator), as shown in Fig. 8. k ω p and k ω i are the proportional and integral constants of the speed regulator. The output of the speed regulator is the reference q-axis current (i q * s ).  Step-5. Filter control strategy: Once v dq * s is generated using step-4, it is compared with the estimated stator voltage (v dq s ) and the respective error voltage (ε dq v s =v dq * s -v dq s ) is regulated by a proportional controller, as mentioned in Fig. 8.v dq s can be estimated using the observer described in Section III-B. The reference value of the capacitor current (i dq * c ) is generated through this proportional controller by selecting the appropriate gain (k  Table I. Step-6: The reference voltage space vector (v dq * i = v d * i + jv q * i ) is converted to v αβ * i as (17) utilizing the estimated rotor angle (ρ ψ r ).ρ ψ r is estimated from the rotor flux space vector (ψ dq r ) as usingρ ψ r = tan −1 (ψ q r /ψ d r ), whereψ dq r is estimated using observer in Section III-B [7].
where |v αβ * i | and δ v are the magnitude and phase of v αβ * i , respectively. Equation (17) indicates that δ v contains the information ofρ ψ r and precisely controls the drive to achieve the desired speed.
Step-7. PWM generation strategy: v αβ * i and the DC-link voltage (v dc ) are further utilized to obtain d ix , as shown in Fig. 6. Using (10)-(11), d ix is converted to the reference value d * ix . The peak value of d * ix is considered as the DC-link voltage utilization ratio (m a ). It can be seen that m a varies in the range of [0,0.5257] according to speed requirements. This performance evaluation is indicated in Section II-B. d * ix then compared with the carrier waveform to generate the switching pulses {S abcde , S a b c d e } to guarantee the operation of the constant switching frequency (f sw ). The carrier waveform is controlled through f sw , which is generated from the switching

B. FPIM Drive Modeling and Observer Design
In order to design the speed observer, the complete FPIM drive modeling including the LC filter is necessary. As mentioned in Section III-A, v αβ i and i αβ i are generated from the measured v dc and i abcd s , using the appropriate transformation given in (16). In αβ-frame, the LC filter output, that is, the stator side voltage (v αβ s ) and current (î αβ s ) can be estimated using the filter inductor (L x f ≈ L f ) and capacitor (C x f ≈ C f ) as (18).
Furthermore,v αβ s andî αβ s are transformed intov dq s andî dq s , by utilizing (16). The electrical parameters are defined in Table I. The equivalent stator and rotor inductances can be represented as L s = L ls + L m and L r = L lr + L m , respectively. Now, the effective stator inductance can be represented as L s = σL s . Here, σ = 1 − L 2 m /L s L r represents the magnetizing coefficient. The variables k s = L m /L s and k r = L m /L r represent the stator and rotor constants, respectively. The stator and rotor time constants can be represented as τ s = L m /L s and τ r = L m /L r , respectively. The effective stator and rotor time constants can be τ s = στ s and τ r = στ r , respectively. By utilizing the voltage model of the FPIM, the phase-variable model of FPIM can be represented as (19). The solution of (19) (ψ dq r i.e., the estimated value of ψ dq r ) can be utilized to estimate dq-frame stator flux (i.e.,ψ dq s ), as given in (20).ψ dq s = k rψ dq r + L s î dq s (20) As per (18) and (20), the errors inî dq i can indirectly reflect in estimatedψ dq s . Let ε dq i i = i dq * i −î dq i be the error in dq-axis stator current. Now, the observer estimated value with (19) can be realized in (21).
where the complex variables μ dq s and μ dq r are the gains of the observer. From (19) and (21) the error dynamics can be incurred as (22).
In order to compensate the uncertainties due to system dynamics, the complex gain μ dq s need to be chosen high enough, i.e., μ dq s 0. Hence, the low frequency variables should converge to zero, i.e., ε dq ψ s → 0 andε dq ψ s → 0. Now, (22) can be reduced to get the low frequency flux error dynamics in (23).
The stability of the designed observer can be analyzed through the Lyapunov candidate function given in (24).
where ρ is a weight variable. The dynamics of Lyapunov candidate function must satisfy the observer reachability criteria of (25).V By solving (23) and (25), the componentsV 1 andV 2 can be obtained as (26).
To avoid oscillation during speed error convergence,V 2 must tend to zero. Hence,V 1 must be negative definite to satisfy (25). This means that the variable δ must always be negative. Now, the complex gains can be obtained as (27). By solvingV 2 = 0 using (26), the speed dynamic error can be obtained as (28).
where p is the number of FPIM pole pairs.ε m ω is the mechanical speed dynamic error and can be defined as (29).
where ω * m is the reference speed command andω * m can be obtained by utilizing a tracking differentiator (TD) to ω * m . By solving (28) and (29), the dynamic in estimated motor speed (ω m ) can be obtained as (30).
From the mechanical dynamics of FPIM,ε m ω can be derived as (31).ω where B and J denote the damping coefficient and moment of inertia of FPIM. The estimated electromagnetic torque (T e ) of FPIM can be obtained by (32).
The estimated value of the load torque (T L ) applied to FPIM can be obtained from the load torque dynamics given in (33). where k t is a gain variable. Solving (30) and (31),ω m can be obtained as (34).
The estimated value of the rotor position (θ r ) can be obtained from (35).θ Further,θ r is utilized for αβ-dq transformation as mentioned in Section III-A. The speed observer performance depends on the parameters, which again considers all parameter variations as disturbance and estimates the speed most accurately. The detailed structure of the observer is provided in Fig. 9.

IV. RESULTS AND ANALYSIS
The prototype experimental setup is shown in Fig. 10 for the SEMIKRON IGBT (SKM100GB063D) based FPTL VSI to validate the proposed FOC-based switching loss control scheme under various PWM (SVPWM, CPWM, DPWM) methods. An on-board LC filter is implemented for better electromagnetic interference (EMI) control. The inductor core for L f is made of EI133 grade ferrite material. Due to the smaller size of L f and the wider range of switching frequency, the power density of the inverter is markedly improved. The OPAL-RT OP5700 [inbuilt digital signal processor (DSP) and field-programmable gate array (FPGA)] controller is used to implement the control structure and the Xilinx XC7Z020 FPGA controller is used to obtain the output of the switching pulse. The maximum and minimum sampling frequencies of the controller are fixed at 500 kHz and 100 kHz, respectively. A fixed 100 kHz sampling frequency is used for the control of FPTL VSI. A 3.8 kW FPIM is coupled to a 5 kW separately excited dc generator for loading. Both the mechanical and electrical specifications of the FPIM are summarized in Table I. A voltage sensor (LEM LV25P) and four current sensors (LEM LA55P) are used as feedback signals through an integrated ADC of the OPAL-RT. A solid-state relay-based contactor is used to isolate the power source when a fault occurs on a VSI or FPIM fault. For recording and evaluating the results, the digital storage oscilloscope (Yokogawa DLM 2034) is used.
Three separate sets of test scenarios have been designed to implement and evaluate the proposed FOC switching loss control scheme for different PWM methods. During these studies, the condition for lowering CMV and maintaining a constant f sw through adaptive switching loss control is satisfied.

A. Scenario-1:Acceleration and Low Speed Performance
This test condition is designed for T L = 0 → 10 Nm, ω * m = 0 → 200 rpm→ 1200 rpm→ 0 rpm and the corresponding outcome for the proposed FOC with switching loss control based on SVPWM, CPWM, and DPWM is shown in Figs. 11-13 respectively. The drive acceleration and low speed performance can be observed in Fig. 11 for the SVPWM scheme, by varying the speed from zero to 1200 rpm with two steps at t = t 1 = 200 rpm and t = t 2 = 1200 rpm, and finally getting to zero rpm. Moreover, the load torque is varied from zero to 10 Nm at t = t 1 s. It is observed that the performance indices of drive torque (T e ), mechanical drive speed (ω m ), error in speed (ω err ), and switching losses of VSI (P sw ) are represented from top to bottom, respectively, in the corresponding graphs. Therefore, it can be observed that the proposed switching loss FOC control scheme for the SVPWM method accurately tracks the reference speed and torque, and the speed error is very minimal. Acceleration, as well as deceleration, is being performed impressively with low speed operation. During deceleration, the torque transition shows a negative torque, which indicates that the drive is in regenerative mode. The switching loss for this method is observed at the bottom of Fig. 11(a), and it can be observed that P sw is minimal. Figs. 12 and 13 show the acceleration and low speed performance of the proposed FOC with switching loss control for the CPWM and DPWM methods, respectively. Like the SVPWM scheme, CPWM and DPWM provide good acceleration and low speed performance by tracking speed and torque reference accurately with a little more torque ripple compared to SVPWM. Furthermore, during acceleration (during t = t 1 s and t = t 2 s), DPWM has more torque ripple compared to CPWM and SVPWM. With regard to low-speed operation (during t = t 3 s), both methods provide better performance. However, the CPWM

B. Scenario-2: Speed Reversal and Low Speed Operation
The proposed FOC based on switching loss control with SVPWM, CPWM, and DPWM is evaluated in this test condition to find the speed reversal and low speed performance of the drive. For this, the test conditions are considered as T L = 0 → 5 Nm, ω * m = 0 → 600 rpm→ −300 rpm→ 0, and the results are presented in Figs. 14-16. Speed reversal is one of the dynamic operating conditions for evaluating drive dynamics, which is initiated by changing the reference speed from 600 rpm to −300 rpm at time t = t 2 s with a load torque of 5 Nm and shown in Fig. 14(a) for the proposed SVPWM method. It can be observed that the speed reversal of the drive is very smooth and the corresponding drive torque, the speed error, is tracking their reference values with minimal deviations. The switching loss characteristics for the same are shown in Fig. 14(a) bottom, which is less than compared to the CPWM and DPWM methods ( Fig. 15(a)) and Fig. 16(a)). Low speed performance can be observed in the speed reversal itself, where the speed of the drive changes from 600 to -300 rpm, at zero crossing or nearly zero crossing of the speed. Due to the proposed controller, the demagnetization effect under low-speed operation is nullified by selecting the appropriate voltage vectors. This can be observed in the stator flux trajectories, which are constant throughout the operation and are shown in Fig. 14(b).
Similarly, the speed reversal and low-speed operation of the FOC controlled two-level fed FPIM drive for CPWM and DPWM are presented in Figs. 15(a) and 16(a). The results look similar to those of the SVPWM method, but the switching losses are in both cases compared to the SVPWM (DPWM > CPWM). The stator current and flux trajectories in the αβ plane are shown for all three proposed FOC with switching loss control based on SVPWM, CPWM, and DPWM are shown in Figs. 14(b), 15(b), and 16(b), respectively. It is observed that the proposed SVPWM has less current ripple compared to the proposed CPWM and DPWM PWM schemes. Coming to the stator flux, in all three methods, the flux is kept constant and has less ripple in the SVPWM scheme over the CPWM and DPWM.

C. Scenario-3: Load Variation Performance
In this case, the drive is tested on load rejection properties by varying the load torque of T L = 10 Nm → 20 Nm→ 10 Nm with a constant speed reference of 1500 rpm. First, the drive runs at a rated speed with a load torque of 10 Nm, then at t = t 1 s the load torque increases from 10 Nm to 20 Nm. Later, the load torque is reduced from 20 Nm to 10 Nm at time t = t 2 s, as shown in Figs. 17(a), 18(a), and 19(a) for the proposed SVPWM, CPWM and DPWM schemes. It is observed that the drive is capable of handling the load in all three cases very smoothly, even if a sudden load change occurs. Furthermore, it can be observed that the drive speed is maintained constant throughout the operation with minimal speed error (ω err ). The proposed FOC with SVPWM switching loss control has a lower switching loss under load variation (from t = t 1 → t 2 s) over the CPWM and DPWM (DPWM> CPWM).
The stator current and flux trajectories for all three methods are shown in Figs. 17(b) and 18(b) and Fig. 19(b). It is observed that the stator flux is constant and maintained in the circle throughout the operation with a ripple-increasing manner for SVPWM, CPWM, and DPWM. The stator currents are regulated according to the load and have a lower ripple content in the SVPWM than the CPWM and DPWM. From these test conditions, it is concluded that the drive is tested in both steady-state and dynamic conditions with various tests. The comparison charts and conclusions are made in the following comparison section.

D. Filter Performance Analysis
The drive performance with the filter effect in terms of input line voltage (v ab i ), stator line voltage (v ab s ), and phase voltage (v a s ) and phase current (i a s ) are presented in Figs. 20-22 for SVPWM, CPWM, and DPWM, respectively. The drive is operated under two different loading conditions (T L = 20 Nm and T L = 10 Nm) at constant speed. It is observed that the SVPWM based FOC scheme provides smooth voltage and current waveform after filtering, which is nearly sinusoidal,

E. Comparison Performance
The proposed FOC with a switching loss control based on the SVPWM (SVPWM-FOC), CPWM (CPWM-FOC), and DPWM (DPWM-FOC) schemes is compared and presented in Fig. 23. The performance indices are dc-link voltage utilization, switching loss comparison, switching frequency comparison, and total harmonic distortion (THD) comparison. The dc-link voltage utilization plot is shown in Fig. 23(a) for the SVPWM method, which is achieved between the per-unit speed (k ω ) versus modulation index (m a ). The voltage utilization is observed to depend on both the drive speed and the modulation index of the proposed SVPWM, CPWM and DPWM methods. The dc-link voltage utilization for all these three methods is nearly the same; hence, it is not shown for the other two methods. The variations of switching loss (P sw ) and switching frequency (f sw ) variations at different operating speeds are plotted in Fig. 23(b) for the SVPWM-FOC, CPWM-FOC, and DPWM-FOC schemes. The plot (solid blue line) corresponding to SVPWM-FOC represents that the drive operates with a 1.9 kHz switching frequency and contributes 66 kW of switching loss at 50% of the rated speed, that is, k ω = 0.5. Similarly, it can be seen that the graphs corresponding to CPWM-FOC (green dotted line) and DPWM-FOC (pink dotted line) are used to interpret both f sw and P sw in Fig. 23(b). The scale of P sw is adjusted in correlation with the available data for f sw ∼ k ω . The proposed SVPWM-FOC scheme has lower switching losses over the other two proposed CPWM-FOC and DPWM-FOC schemes (CPWM-FOC < DPWM-FOC). It can be concluded that the switching losses are lower at low PU speed. At higher operating speed, switching losses are more compared to lower operating speed. The THD vs. modulation index is plotted in Fig. 23(c) for the proposed FOC with switching loss control for SVPWM, CPWM, and DPWM. It is observed that the THD of SVPWM scheme is lower than the other two methods; this is due as the SVPWM scheme eliminates the harmonic content in the output voltage and current. As the modulation index increases, the THD value gets lower and lower. Hence, it is concluded that the proposed FOC with switching loss control method based on SVPWM, CPWM, and DPWM provides better speed torque characteristics under various testing conditions with low switching loss and better THD. Of all, the SVPWM scheme has better performance than the CPWM and DPWM schemes.

V. CONCLUSION
Controlling switching losses in an FPTL-VSI-fed drive with continuous and discontinuous SVPWM has been demonstrated. This paper includes a detailed analysis of the proposed current ripple analysis to control the switching loss. In terms of stability and dynamic response, the prototype with an optimum switching frequency scheme performs well. For the FPTL VSI-fed FPIM drive, the zero-sequence injection scheme is proposed to form SVPWM, CPWM, and DPWM, which can be implemented in the full speed range. The hardware results of the prototype have been validated using the proposed method, including CPWM and DPWM. Compared to traditional inverters with fixed switching frequencies, the efficiency and power density of the proposed method are significantly higher. Further, the effects of parasitic, parameter dependencies, and noise filtration on the switching frequency estimation of LC-filter based FPIM drives is a potential subject for the future consideration.