ULTRARAM: Toward the Development of a III–V Semiconductor, Nonvolatile, Random Access Memory

ULTRARAM is a III–V compound semiconductor memory concept that exploits quantum resonant tunneling to achieve nonvolatility at extremely low switching energy per unit area. Prototype devices are fabricated in a <inline-formula> <tex-math notation="LaTeX">$2\times2$ </tex-math></inline-formula> memory array formation on GaAs substrates. The devices show 0/1 state contrast from program/erase (P/E) cycles with 2.5 V pulses of 500-<inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> duration, a remarkable switching speed for a <inline-formula> <tex-math notation="LaTeX">$20~ \mu \text{m}$ </tex-math></inline-formula> gate length. Memory retention is tested for <inline-formula> <tex-math notation="LaTeX">$8\times 10^{4}$ </tex-math></inline-formula> s, whereby the 0/1 states show adequate contrast throughout, whilst performing <inline-formula> <tex-math notation="LaTeX">$8\times 10^{4}$ </tex-math></inline-formula> readout operations. Further reliability is demonstrated via program-read-erase-read endurance cycling for <inline-formula> <tex-math notation="LaTeX">$10^{6}$ </tex-math></inline-formula> cycles with 0/1 contrast. A half-voltage array architecture proposed in our previous work is experimentally realized, with an outstandingly small disturb rate over <inline-formula> <tex-math notation="LaTeX">$10^{5}$ </tex-math></inline-formula> half-voltage cycles.

of the 6.1-Å semiconductor family (InAs, AlSb, and GaSb) [3]. In particular, the extraordinarily large conduction-band offset of InAs/AlSb (2.1 eV) delivers electron barriers akin to those of dielectrics to achieve nonvolatility. In common with flash, the logic state is defined by charge (electrons) stored within a floating gate (FG). However, in ULTRARAM electrons are transported into and out of the FG via triple-barrier resonant tunneling (TBRT) structure formed from InAs/AlSb heterojunctions [4]. This resolves the paradox of universal memory, as the tunneling structure provides a high-energy barrier when there is no bias applied, but allows resonanttunneling (i.e., transparent barriers) at program/erase (P/E) voltages of around 2.5 V, approximately ten times lower than flash. These characteristics are predicted by simulations of quantum transport [5] and have previously been demonstrated in single devices at room temperature [6]. The intricate physics of the tunneling mechanism used here and a comparison of ULTRARAM with current and emerging memory technologies are described in detail in our previous work for the interested reader [5]. Additionally, the devices out-perform other resonant-tunneling-based memories in endurance benchmarks with at least a similar logic retention time [7], [8]. Most importantly, the FG design allows for high-density array architectures and the possibility of vastly improved readout (1/0) contrast [5]. Moreover, the current through the gate during P/E cycles is extremely small, significantly reducing memory power consumption by comparison.
Initial prototype single-cell devices [6] exhibited a limited endurance despite the extraordinary InAs/AlSb conduction band offset and switching at extremely low voltages. This was undoubtedly the result of a large (milliampere) hole leakage current passing from the control gate (CG) terminal to the source/drain (S/D) terminals due to the low valence band offset of the InAs/AlSb heterojunction of just 0.1 eV. Here, the design is amended to include an Al 2 O 3 gate dielectric formed via atomic layer deposition (ALD). This layer provides the necessary band offsets with InAs to block all carrier flow through the CG [9] but requires the memory tunneling structure to be reversed such that tunneling for P/E cycles occurs from the source of the cell (Fig. 1).

TABLE I CROSS-SECTIONAL TEM MEASUREMENTS
GaAs wafers by molecular beam epitaxy (MBE) on a Veeco GENxplor system. The 7.8% GaSb/GaAs lattice mismatch was mitigated by the use of an interfacial misfit array between the substrate and GaSb buffer layer [10] before the growth of the GaSb/InAs/AlSb memory structure. Layer thicknesses are measured via cross-sectional transmission electron microscopy (TEM) with the crucial TBRT structure thicknesses listed in Table I.
Memory arrays were processed on the MBE-grown wafer using a top-down approach (Fig. 1). Devices were fabricated using standard photolithography techniques. Inductively coupled plasma (ICP) etching with BCl 3 /Cl 2 /Ar gas mixtures was used to access the back gate (BG) layer. In situ reflectance monitoring allowed etching to cease accurately in the desired layer. In order to reveal the channel layer, an alternating selective wet etch was employed to etch each layer in succession. Microposit MF-319 (tetramethylammonium hydroxide) was used to selectively etch AlSb and GaSb over InAs [11], and a citric-acid-based etchant (C 6 H 8 O 7 :H 2 O 2 :H 2 O) was used to selectively etch InAs over AlSb and GaSb. Contacts joining D-BG-D along with S terminals were fabricated via Ti-Au sputtering through lift-off resist windows. The memory design utilizes a gate-last approach, where the ALD-Al 2 O 3 layer was deposited over the surface prior to metal CG layers being added. This was followed by further SiO 2 passivation via plasma-enhanced chemical vapor deposition. Last, the device CG, S, and BG terminals were revealed once more by buffered HF etching of the Al 2 O 3 and SiO 2 layers, before depositing  metal Ti-Au contact pads. A scanning electron microscope image of the fabricated arrays is shown in Fig. 2, where word lines (WLs) connecting CG terminals pass across the array horizontally. Bit lines (BLs) connecting S terminals are situated vertically in the image, separated from the underlying WL contact by the SiO 2 layer. Fig. 3 presents the current flow from S to D during an S-D voltage sweep after a 500-μs, −2.5-V program cycle (red) and a 500-μs, +2.5-V erase cycle (black) applied to the S terminal of a 20-μm-gate-length cell within a 2 × 2 memory array. Such a P/E cycle corresponds to a 10 2 and 10 3 reduction in switching energy per unit area compared to DRAM and NAND flash, respectively [12]. There is clear state contrast between 0/1 following the P/E cycles. Overall current is significantly reduced compared to the previous iteration of the technology [6], due to the introduction of the Al 2 O 3 gate dielectric. Moreover, CG-D resistance is improved from 10 3 to >10 10 (the limit of measurement). Within the array, architecture S-D current (I S−D ) is measured via the BG terminal as the D terminals are buried within the random access memory (RAM) architecture [5], as shown in Fig. 1.

III. LOW VOLTAGE P/E
The speed of the P/E cycle is noteworthy, and is 2000× faster than previous devices [6]. As the speed of quantum tunneling is in the sub-picosecond scale [13], the switching speed is limited by the RC time constant, and is, therefore, subject to Dennard's scaling law (scaling linearly with the area) [14]. Thus, for a 20-nm gate length device with ideal scaling subnanosecond switching speed is predicted-significantly faster than DRAM and comparable to static RAM (SRAM) [1], [2], [12]. However, rigorous testing on small-scale devices is required to confirm this.
P/E cycles at ±2.5 V were carried out by applying the voltage pulse to the BL whilst grounding the WL of the target device. The other cell on the array which shares this BL is undisturbed as its CG terminal is floating. Previously, a halfvoltage architecture was proposed in which individual memory cells are selected by applying half of the required P/E voltage to the WL and the other half to the BL [5]. It is found that the same 0/1 contrast can be obtained using this P/E scheme, whereby ±1.25 V pulses applied to BL and WL are used to cycle the memory state. A disturbance test consisting of an uninterrupted ±1.25 V bias was applied separately to BL and WL in both 0 and 1 states for 120 s, equivalent to 10 5 P/E cycles, and did not perturb the memory state from a 0 or 1 logic position.
The results presented in Fig. 3 show a clear, measurable difference between the 0 and 1 states. However, if potentially 1000's of cells are to be connected in a single BL in the future, a dramatic improvement in read contrast (0/1) is of paramount importance [12]. Fortunately, the insufficient read contrast is not an indication of logic state weakness, but rather due to the simplicity of the channel construction. The channel of the memory cells is formed from an n-doped InAs layer and is, therefore, normally-ON. It is partially depleted by the presence of FG charges, resulting in a measurable, but limited, change in channel conductivity. Work is ongoing to incorporate the normally-OFF InGaAs channel design described in our previous work [5] to address this issue. Producing a thresholdvoltage-based readout scheme should dramatically improve readout contrast allowing larger memory arrays. Although the P/E cycling scheme for the RAM architecture presented in [5] has been confirmed, the readout contrast and uniformity in channel conductivity are not sufficient to reliably test device-to-device switching in the array formation. While the insufficient contrast is due to the channel construction, the variation in the channel conductivity is a result of a  suboptimal etching procedure (discussed in Section IV). As such, tests are carried out on a single device within the array formation, with surrounding devices ignored. Typically, FG-storage memories such as flash suffer from poor endurance (i.e., degradation due to many P/E cycles), such that wear-leveling is required to prolong their lifetime [15]. Wear leveling is unsuitable for RAM, which requires superior endurance properties, with individual cells being programed and erased with each computational operation. In this work, ULTRARAM cells withstood 10 6 P/E (P-read-E-read) switching cycles [ Fig. 5(a)], whilst maintaining a clear 0/1 state contrast. P/E cycling was performed at a rate of 200 cycles per minute with 5 ms P/E pulses, except for the blue shaded region, where it was shortened to 500 μs, reducing the 0/1 contrast. The reason for this reduction is the significant RC time constant due to the device feature size (i.e., the gate-stack potential does not reach 2.5 V within the pulse). The tunneling mechanism itself is intrinsically extremely fast [5].

IV. RELIABILITY
In this first-ever test, endurance is at least an order of magnitude higher than flash memory [2]. There is, however, movement of the 0/1 window throughout the process. The reason for this is currently unknown, but it is thought that it may be a result of an inconsistent channel contact that is sensitive to temperature or vibrations. Atomic force microscopy of the wet-etched channel surface shows significant etch pitting, which could cause intermittent contact with the underlying layers. An ICP etch process to create a smooth surface for consistent contact to the thin (10 nm) channel material is currently being developed in response. Fluctuations in I S−D offset aside, a memory is realized for over 10 6 cycles (Fig. 5). Moreover, the difference in current between 0 and 1 [I S−D , Fig. 5(b)] persists throughout the endurance test with the P and E states tracking each other. Despite the inconsistencies in overall current, Fig. 5(b) shows a significant 0/1 state contrast over the 10 6 logic-switching cycles.

V. CONCLUSION
We have experimentally confirmed the principles required for a RAM using the III-V ULTRARAM memory concept within cells of 2 × 2 arrays. Cells can be programed and erased at extremely low switching energy (per unit area) using a halfvoltage architecture in which the P/E voltage is split between BL (S) and WL (CG). The logic states of cells within this architecture are shown to be disturb-free for the equivalent of at least 10 5 cycles. An up to 2000× improvement in switching speed compared with previous devices is demonstrated, with P/E at ≥500 μs for a 20 μm gate length. Assuming capacitive scaling, this predicts sub-nanosecond operation at the 20 nm node. Highly robust retention of both states is established for 8 × 10 4 s with 8 × 10 4 reads, limited only by the length of the experiment. Memory cells can withstand 10 6 P/E cycles without degradation, thus the benchmark for endurance exceeds that of flash and many resistive-memory technologies. As a result, fast, ultraefficient, nonvolatile, random access ULTRARAM memories are a real possibility.

ACKNOWLEDGMENT
The data in the figures of this article are openly available from Lancaster University data archive in [16].