Resistive Switching Device Technology Based on Silicon Oxide for Improved ON–OFF Ratio—Part I: Memory Devices

Resistive switching memory (RRAM) is among the most mature technologies for next generation storage class memory with low power, high density, and improved performance. The biggest challenge toward industrialization of RRAM is the large variability and noise issues, causing distribution broadening which affects retention even at room temperature. Noise and variability can be addressed by enlarging the resistance window between low-resistance state and high-resistance state, which requires a proper engineering of device materials and electrodes. This paper presents an RRAM device technology based on silicon oxide (SiOx), showing high resistance window thanks to the high bandgap in the silicon oxide. Endurance, retention, and variability show excellent performance, thus supporting SiOx as a strong active material for developing future generation RRAMs.


I. INTRODUCTION
R ESISTIVE switching memory (RRAM) devices are promising for future replacement of nonvolatile high-density memories, such as Flash and storage class memory (SCM), the latter combining the high density and low cost of Flash memory with the short latency and random bit access of RAM [1]. Although RRAM has been raising a strong interest, the reliability aspects have prevented the development of a commercial technology so far. In particular, RRAM generally suffers from programming variability [2]- [4] and noise-induced distribution broadening [3], [5], [6], which significantly limit retention in large arrays even at room temperature.
To mitigate the impact of noise on programmed distributions, the intrinsic resistance window of the RRAM device must be improved. For instance, RRAM devices based on metal cation migration, also known as conductive-bridge RAM (CBRAM) devices, have shown improved resistance window compared with the conventional metal-oxide RRAM [7], mainly thanks to a high-resistance state (HRS). Alternative schemes to improve the resistance window include the use of relatively high compliance current I C to lower the low-resistance state (LRS) resistance, however, causing a corresponding increase of current consumption [8]. Enhancing and controlling the HRS resistance seem thus essential to improve RRAM reliability. This paper presents a new RRAM device technology based on silicon oxide, i.e., SiO x with x ≈ 1. The device shows bipolar switching with high resistance window, reaching a ratio of about 10 4 between HRS and LRS despite a low compliance current I C = 50 µA. The device also shows excellent reliability, including high endurance (above 10 7 cycles), small variability, and good retention (1 hour at 260°C). These data fully support SiO x memory technology as a promising candidate for future SCM and embedded RRAM [9], [10].
A preliminary study of the SiO x devices was previously reported in [11]. Here, we provide a fully detailed report, further exploring the thickness dependence, the voltagecontrolled overshoot and endurance, and the impact of I C scaling. While this paper addresses the switching and reliability characteristics of SiO x memory, the companion paper presents volatile switching in SiO x -based devices with potential application as selectors in crossbar arrays [12]. Fig. 1(a) shows a schematic illustration of the RRAM device studied in this paper. In the RRAM device, the switching layer consists of SiO x as in previous RRAM works [13], [14].

II. EXPERIMENTAL DEVICES AND SETUP
The SiO x switching layer was deposited by e-beam evaporation from a silicon monoxide source, thus x ≈ 1. The Ti top electrode (TE) was e-beam evaporated without breaking the vacuum from the previous SiO  bottom electrode with a diameter of 70 nm. Below the C electrode, a W-plug served as via to an integrated select transistor in the front end. The availability of an integrated transistor enables independent selection of any RRAM device and control of the compliance current I C during set transition with negligible parasitic capacitance [15], [16]. The Ti thickness was usually 50 nm, while SiO x was deposited with various thicknesses t ox between 1.5 and 6.5 nm to optimize the switching and forming characteristics. Atomic force microscopy (AFM) was used to characterize t ox on control samples by measuring the AFM profile over a step obtained with a shadow mask [11].
The experimental setup sketched in Fig. 1(b) included both a semiconductor parameter analyzer for DC measurements and an arbitrary waveform generator with an oscilloscope to test the pulsed characteristics. In both cases, the one-transistor/ one-resistor (1T1R) structure was characterized by controlling both the gate and the TE voltage with source grounded. The AC current was measured at the source side via the voltage drop across the 50-input impedance of the oscilloscope during pulsed measurements.

III. FORMING AND SWITCHING CHARACTERISTICS
Devices were characterized by first applying a forming step with positive voltage aiming at inducing the injection of cations from Ti to form a conductive filament (CF). The CF was then retracted to the TE by the application of a negative voltage in the reset operation. Positive set and negative reset processes were then operated in DC or AC mode to study bipolar switching.
We attribute resistance switching in our devices to Ti cation migration originated from the TE during forming. Cation migration is usually assumed to take place in CBRAM-type devices with Ag/Cu containing TE [17], [18]. However, it was long been postulated that other metals, such as Ti, Ta, and Hf, could lead to migration in oxide-based RRAM [19], which was recently shown by experiments [20]. Moreover, our devices did not show any forming even for negative voltages up to −10 V. This is a further reason to believe that the resistance switching in our devices can be explained by Ti cation migration within a Ti-rich CF, where the lower mobility of Ti and the higher chemical interaction between Ti and SiO x can be responsible for lower variability and improved retention with respect to more conventional Ag-and Cu-based CBRAM [18]. However, we cannot rule out that oxygen vacancy and silicon nanoinclusions contribute to the switching process in our samples, as proposed in other SiO x -based RRAM [14]. Fig. 2(a) shows the typical I-V curves of forming, set, and reset transitions for an RRAM device with SiO x thickness t ox = 3 nm. The forming process takes place at relatively large positive voltage V form . After the forming process, the device starts to reset at a negative voltage V reset . The device shows an incremental reset transition, where resistance increases at increasing voltage as a result of the increasing length of the depleted gap 1 and the decreasing density of defects within 1 [21]. The HRS resistance thus depends on the maximum negative voltage V stop , which is applied during the reset transition. Application of a positive voltage to the LRS shows a set transition, consisting of an abrupt increase of current at a voltage V set . Despite a large resistance window of about 10 4 in Fig. 2(a), the HRS resistance is smaller than the initial resistance of the device in the pristine state. Fig. 2(b) shows the typical I-V curves for set and reset transitions for SiO x thickness t ox = 1.5, 3, and 6.5 nm, while Fig. 2(c) summarizes the forming, set, and reset voltages as a function of t ox . The forming voltage increases linearly with the oxide thickness, in accordance to a field-driven oxide breakdown model, such as the E model [22] or the 1/E model [23]. The estimated breakdown electric field for the SiO x layer is 13.1 MVcm −1 . On the other hand, V set and V reset show a slight increase with t ox . The decrease of V set with thickness can be attributed to the decrease of HRS resistance, which is visible in Fig. 2(b) for t ox = 1.5 nm and might be explained by the depleted width 1 being limited by t ox .F o r t ox = 6.5 nm, the device tends to exhibit current overshoot, evidenced by the reset current I reset being higher than I C . Current overshoot might be due to the relatively large value of V set causing fast transition to LRS before the voltage snap back in the 1T1R structure can take place [16]. The best tradeoff between HRS and LRS control was obtained at t ox = 3 nm, which was thus taken as a reference case for the following in-depth analysis of the switching characteristics of RRAM devices. Fig. 3(a) shows the measured I-V curves for increasing V stop in SiO x RRAM devices with t ox = 3 nm. A single device was cycled 20 times for each V stop , starting from V stop =−4.5V and gradually decreasing |V stop |toward− 2.5 V. A compliance current I C = 70 µA was used during forming and during all set processes. The resistance window can be effectively increased with V stop , as shown by the measured HRS and LRS resistance values in Fig. 3(b). While HRS resistance increases, LRS resistance decreases at increasing amplitude of V stop , probably due to the increasing value of V set as shown in Fig. 3(c).A sV stop increases, the concentration of defects within the depleted gap length 1 decreases [21], and thus, the leakage current decreases and the corresponding V set increases. Al a r g e rV set causes moderate current overshoot with a small   decrease of LRS resistance, although I reset never exceeds I C by more than 20% [ Fig. 3(c)].

B. Impact of V stop
C. Impact of I C Fig. 4(a) shows the measured I-V curves for increasing I C , which was changed by varying the gate voltage V G applied to the transistor in the 1T1R structure. Fig. 4(b) shows the measured R as a function of I C for LRS and HRS. All devices were initially formed at I C = 20 µA, and then, set/reset experiments were conducted at increasing I C .L a r g e r values of I C result in smaller LRS resistances in the range between 10 and 100 k, revealing an increasing size of the CF, while the HRS is negligibly affected. The LRS resistance decreases as R ≈ V C /I C , where the characteristic voltage V C for ion migration is around 1.1 V, in agreement with previous results [19]. This is the voltage needed to induce ion migration in the timescale of the experiment, which was about 1 s in this paper. Interestingly, V C ≈ 1.1 V is very close to the absolute value of V reset in Figs. 3 and 4, revealing polarity-independent ion migration in SiO x [21]. Fig. 5(a) shows the cumulative distributions of measured R for LRS at increasing I C and HRS at increasing V stop . Data generally show a good control of resistance levels by varying either I C or V stop , which is promising for multilevel cell operation of SiO x -RRAM devices. However, distributions show a significant statistical spread, which can be quantified by the standard deviation σ R . Fig. 5(b) shows the relative spread σ R /R, which is generally considered a figure of merit for the variability of set/reset processes in RRAM [3], [4]. The relative standard deviation σ R /R is shown as a function of R and compared with HfO x RRAM [3]. Both LRS data at variable I C and HRS data at variable V stop are reported. LRS shows similar variability in SiO x and HfO x , suggesting a common origin of the CF, such as metallic-type defects, e.g., Ti or Hf. In both cases, LRS variability shows a linear dependence with resistance, namely σ R /R ≈ R, which can be attributed to defect shape variation in the CF [3], [4]. On the other hand, HRS shows markedly different variabilities in the two materials, with SiO x displaying approximately constant σ R /R ≈ 1, hence much smaller than HfO x . Given the strong impact of HRS variability on RRAM array reliability, these data suggest that SiO x is much more promising than HfO x in the view of the higher resistance window and decreased variability.

IV. PULSED CHARACTERISTICS
We characterized RRAM devices in the pulsed regime by applying triangular set and reset pulses with pulsewidth t P = 100 µs using the setup in Fig. 1(b). Fig. 6(a) shows the typical voltage and current traces of set and reset operations. Different gate voltages were applied for the set pulse (V G = 1.2 V, resulting in a compliance current I C = 50 µA) and the reset pulse (V G = 2.5 V, thus limiting the transistor series resistance to maximize the voltage drop across the RRAM device). Peak voltages V + = 4Va n dV stop =−3.5V were used in the two pulses. During the positive voltage pulse, an abrupt current increase can be observed, corresponding to the set transition to LRS. During the negative voltage pulse, before the maximum voltage V stop is reached, the reset process starts occurring, resulting in a gradual decrease of current, bringing the device back to HRS. The corresponding I-V curves can be reconstructed by merging the voltage and current traces together, as shown in Fig. 6(b) [24].
The pulsed regime behavior of SiO x devices was studied by applying pulse trains with V stop varying from −2t o−3.5 V with 0.5-V steps, to characterize the resistance window opening. For each V stop , 1000 set-reset cycles were applied to the memory cell. Fig. 6(c) and (d) shows the distributions of measured resistance of LRS and HRS. As for the DC case, increasing |V stop | causes a slight decrease of LRS resistance and a strong increase of HRS resistance, thus leading to an enlargement of the resistance window by one order of magnitude on average. In pulsed regime, however, experimental noise strongly influences the oscilloscope readout, both in terms of the maximum readable HRS value, which may be underestimated for higher values of |V stop |,andalsointermsof spreading in the HRS distributions, which is larger compared with the DC regime. Moreover, measured HRS values are inherently lower when compared with the corresponding DC readings; this is a well-known effect for resistive switching devices based on ion migration, as the maximum V stop voltage needed to fully reset the devices increases by decreasing the pulsewidth [25]. Data in Fig. 6 again show that LRS resistance decreases at increasing V stop , which was attributed to a moderate overshoot effect in Section III-B.
To better understand the LRS dependence on V stop , Fig. 7(a) shows the measured LRS resistance as a function of V set and for different |V stop | values, indicating that, even for a given V set value, R decreases at increasing V stop .T h i si s different from usual overshoot effects, where R decreases at increasing V set because of the switching time becoming shorter than the electrical RC constant [16], [26]. We attribute this new type of overshoot to the local electric field at set transition. In fact, as V stop increases, the concentration of defects within the depleted gap length 1 decreases, thus causing a decrease of conductance in the depleted gap. This is schematically shown in Fig. 7(b). As a result, the electric field F across the depleted gap increases with V stop [Fig. 7(c)], even for a fixed V set .T h e high internal field induces a stronger migration at the onset of set transition, resulting in a bigger CF and a lower R,w h i c h can explain the slight overshoot effect in Fig. 7(a).

V. R ELIABILITY STUDY
For adoption as SCM or embedded nonvolatile memory, SiO x RRAM must satisfy not only switching window, variability, and noise requirements, but also endurance and temperature-dependent retention criteria. For instance, application as embedded memory requires that the written data survive the thermal budget of the soldering reflow, typically few minutes at 260°C [27], [28]. The reliability of SiO x RRAM devices was studied from the point of view of both data retention at high temperature and endurance.

A. High-Temperature Retention
To study data retention in SiO x RRAM, we prepared three RRAM devices in various LRSs at increasing I C = 10, 25, and 60 µA, while other three devices were prepared in various HRSs at increasing V stop =− 3, − 4, and −4.5 V. After this preliminary stage, the devices were annealed at constant temperature T a = 120°C for 1 h, and then, the resistance of each device was measured to check for variations. Preannealing and postannealing measurements were both done at room temperature to prevent resistance differences due to T-activation of conduction [29]. The annealing/read process was repeated eight times, each time increasing T a by 20°C up to a maximum value of T a = 260°C. Fig. 8(a) shows the measured R as a function of T a , including initial values before annealing. HRS shows a weak decrease of R toward LRS, which might be explained by redistribution of defects into the depleted gap from the top and bottom residual fractions of the CF. Even at the highest T a in the experiments, R decreases by about one order of magnitude, thus revealing a good retention at high temperature. On the other hand, LRS shows a weak increase of resistance toward HRS, the larger drift occurring at the highest R as previously explained by size-dependent retention in RRAM [30]. Such strong retention of LRS is also very promising, given that LRS retention is regarded as particularly critical because of the filamentary nature of the RRAM device [4]. As a reference, HfO x -based RRAM shows weaker LRS stability, with a drift by a factor 2 in 1 h at 250°C for a smaller resistance R = 5k, corresponding to a larger CF than in this paper [31]. The better stability at high temperature might be attributed to the chemical interaction between Ti and SiO x , where Ti can form both TiSi silicide and several Magneli-type compounds with oxygen [32]. Fig. 8(b) shows the I-V curves for the case of V stop =− 4.5 V, measured before and after the full sequence of annealing experiments in Fig. 8(a).T h eI-V curves are negligibly affected by the extensive annealing, suggesting that not only the LRS/HRS are stable over time and temperature but also the structural properties of the thin films remain unaffected.

B. Endurance Characteristics
The endurance characteristics of SiO x devices were studied by applying triangular pulses with pulsewidth t P = 10 µs as described in Section IV. The resistance was measured three times over each decade of cycling by switching from DC to AC and vice versa via the switching matrix setup in Fig. 1(b) This allowed accurate DC measurement of HRS during cycling. Fig. 9(a) and (b) shows the measured R for increasing cycles at V stop =−4Va n d−5 V. The first case corresponds to a relatively low resistance window of about two orders of magnitude, and resulting in a relatively high endurance in excess of 10 7 cycles, with a very clear distinction between HRS and LRS throughout the whole device lifetime. In the second experiment, V stop was increased, which enhances the resistance window to about three orders of magnitude, however, causing a faster degradation and a reduced endurance of about 10 5 cycles. These results are in line with the previously observed tradeoff between resistance window and endurance controlled by V stop [24]. Compared with the HfO x -based RRAM, SiO x displays a much larger endurance at the optimum V stop , which was around 10 6 for HfO x [24].

VI. CONCLUSION
This paper presents a novel Ti/SiO x resistive memory device with high resistive window of four orders of magnitude, extended endurance over 10 7 , and good data retention up to 260°C. The impact of V stop , I C , and oxide layer thickness was studied. The extremely good performance exhibited by the device distinguishes Ti/SiO x as a promising technology for future generation SCM and embedded memory application.